285 lines
10 KiB
Systemverilog
285 lines
10 KiB
Systemverilog
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//For mcu_regfile, the ROreg: mcu_para/rtimr/icntr/fsir are updated by the inputs
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//at this clk_posedge due to dff(inputs->regs)
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class mcu_refmodel;
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virtual mcureg_if mif;
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virtual spi_if wif;
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virtual sram_if#(25,32) xif;
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//poor-quality register model
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bit[31:0] rm[42];
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//members to be sent to scoreboard
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int rst_error[5];
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bit[31:0] dout[$];
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mcureg_trans mcuout[$];
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function new();
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endfunction
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extern task do_imitate();
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extern task RWreg_write (bit[24:0] addr,bit[32:0] din );
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extern task ROreg_update (bit[24:0] addr );
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extern task reg_read (bit[24:0] addr );
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extern task output_trace (bit[24:0] addr );
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endclass : mcu_refmodel
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task mcu_refmodel::do_imitate();
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int i=0,j=0;
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rm[ 0] = 32'h0; //MCUPARAR0
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rm[ 1] = 32'h0; //MCUPARAR1
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rm[ 2] = 32'h0; //MCUPARAR2
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rm[ 3] = 32'h0; //MCUPARAR3
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rm[ 4] = 32'h0; //MCURESR0
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rm[ 5] = 32'h0; //MCURESR1
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rm[ 6] = 32'h0; //MCURESR2
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rm[ 7] = 32'h0; //MCURESR3
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rm[16] = 32'h0; //CWFR0
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rm[17] = 32'h0; //CWFR1
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rm[18] = 32'h0; //CWFR2
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rm[19] = 32'h0; //CWFR3
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rm[20] = 32'h0; //CWPRR
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rm[21] = 32'h0; //GAPR0
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rm[22] = 32'h0; //GAPR1
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rm[23] = 32'h0; //GAPR2
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rm[24] = 32'h0; //GAPR3
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rm[25] = 32'h0; //GAPR4
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rm[26] = 32'h0; //GAPR5
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rm[27] = 32'h0; //GAPR6
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rm[28] = 32'h0; //GAPR7
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rm[29] = 32'h0; //LCPR
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rm[30] = 32'h0; //AMPR0
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rm[31] = 32'h0; //AMPR1
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rm[32] = 32'h0; //AMPR2
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rm[33] = 32'h0; //AMPR3
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rm[34] = 32'h0; //BIASR0
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rm[35] = 32'h0; //BIASR1
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rm[36] = 32'h0; //BIASR2
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rm[37] = 32'h0; //BIASR3
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rm[38] = 32'h0; //RTIMR
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rm[39] = 32'h0; //ICNTR
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rm[40] = 32'h0; //FSIR
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rm[41] = 32'h0; //INTPSELR
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fork
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while(1) begin: write_reg_RW
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@(negedge xif.wren);
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RWreg_write(xif.addr,xif.din);
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end: write_reg_RW
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while(1) begin: update_reg_RO
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@(negedge xif.rden);
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ROreg_update(xif.addr);
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end: update_reg_RO
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while(1) begin: read_reg
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@(negedge xif.rden);
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reg_read(xif.addr);
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end: read_reg
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while(1) begin: output_port
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@(negedge xif.wren);
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output_trace(xif.addr);
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end: output_port
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join
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endtask: do_imitate
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task mcu_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din);
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bit[31:0] wrmask;
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//make mask into 32bit
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wrmask = {{8{mif.wrmask[3]}},{8{mif.wrmask[2]}},{8{mif.wrmask[1]}},{8{mif.wrmask[0]}}};
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//delay caused by decoder
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@(posedge wif.clk);
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case(addr[24: 2])
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23'h1C0004: rm[ 4] = wrmask ? din : rm[ 4]; //MCURESR0
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23'h1C0005: rm[ 5] = wrmask ? din : rm[ 5]; //MCURESR1
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23'h1C0006: rm[ 6] = wrmask ? din : rm[ 6]; //MCURESR2
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23'h1C0007: rm[ 7] = wrmask ? din : rm[ 7]; //MCURESR3
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23'h1C0010: rm[16] = wrmask ? din : rm[16]; //CWFR0
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23'h1C0011: rm[17] = wrmask ? din : rm[17]; //CWFR1
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23'h1C0012: rm[18] = wrmask ? din : rm[18]; //CWFR2
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23'h1C0013: rm[19] = wrmask ? din : rm[19]; //CWFR3
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23'h1C0014: rm[20] = wrmask[0 : 0] ? {din[0 : 0],rm[20][31: 1]} : rm[20]; //CWPRR
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23'h1C0015: rm[21] = wrmask[31:16] ? {din[31:16],rm[21][31:16]} : rm[21]; //GAPR0
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23'h1C0016: rm[22] = wrmask[31:16] ? {din[31:16],rm[22][31:16]} : rm[22]; //GAPR1
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23'h1C0017: rm[23] = wrmask[31:16] ? {din[31:16],rm[23][31:16]} : rm[23]; //GAPR2
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23'h1C0018: rm[24] = wrmask[31:16] ? {din[31:16],rm[24][31:16]} : rm[24]; //GAPR3
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23'h1C0019: rm[25] = wrmask[31:16] ? {din[31:16],rm[25][31:16]} : rm[25]; //GAPR4
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23'h1C001a: rm[26] = wrmask[31:16] ? {din[31:16],rm[26][31:16]} : rm[26]; //GAPR5
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23'h1C001b: rm[27] = wrmask[31:16] ? {din[31:16],rm[27][31:16]} : rm[27]; //GAPR6
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23'h1C001c: rm[28] = wrmask[31:16] ? {din[31:16],rm[28][31:16]} : rm[28]; //GAPR7
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23'h1C001d: rm[29] = wrmask[31:16] ? {din[31:16],rm[29][31:16]} : rm[29]; //LCPR
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23'h1C001e: rm[30] = wrmask[31:16] ? {din[31:16],rm[30][31:16]} : rm[30]; //AMPR0
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23'h1C001f: rm[31] = wrmask[31:16] ? {din[31:16],rm[31][31:16]} : rm[31]; //AMPR1
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23'h1C0020: rm[32] = wrmask[31:16] ? {din[31:16],rm[32][31:16]} : rm[32]; //AMPR2
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23'h1C0021: rm[33] = wrmask[31:16] ? {din[31:16],rm[33][31:16]} : rm[33]; //AMPR3
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23'h1C0022: rm[34] = wrmask[31:16] ? {din[31:16],rm[34][31:16]} : rm[34]; //BIASR0
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23'h1C0023: rm[35] = wrmask[31:16] ? {din[31:16],rm[35][31:16]} : rm[35]; //BIASR1
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23'h1C0024: rm[36] = wrmask[31:16] ? {din[31:16],rm[36][31:16]} : rm[36]; //BIASR2
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23'h1C0025: rm[37] = wrmask[31:16] ? {din[31:16],rm[37][31:16]} : rm[37]; //BIASR3
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23'h1C0029: rm[41] = wrmask[1 : 0] ? {rm[37][31:2 ],din[1 : 0]} : rm[41]; //INTPSELR
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endcase
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@(posedge wif.clk);
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case(addr[24: 2])
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23'h04_0014: rm[12] = 32'b0;
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endcase
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/* $display("mask:%h",wrmask);
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$display("addr:%0h",addr);
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$display("rm[%d]:%h",addr[15:2],rm[addr[15: 2]]);
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$display("din:%h",din);//*/
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endtask: RWreg_write
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task mcu_refmodel::ROreg_update(bit[24:0] addr);
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//@(posedge wif.clk);
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rm[ 0] = mif.mcu_param[0]; //MCUPARAR0
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rm[ 1] = mif.mcu_param[1]; //MCUPARAR1
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rm[ 2] = mif.mcu_param[2]; //MCUPARAR2
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rm[ 3] = mif.mcu_param[3]; //MCUPARAR3
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rm[38] = mif.run_time ; //RTIMR
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rm[39] = mif.instr_num ; //ICNTR
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rm[40] = {rm[32][31:2],mif.fb_st_info[1:0]}; //FSIR
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endtask: ROreg_update
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task mcu_refmodel::reg_read(bit[24:0] addr);
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//delay caused be decoder
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//@(posedge wif.clk);
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case(addr[24: 2])
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23'h1C0000: dout.push_back(rm[ 0]); //MCUPARAR0
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23'h1C0001: dout.push_back(rm[ 1]); //MCUPARAR1
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23'h1C0002: dout.push_back(rm[ 2]); //MCUPARAR2
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23'h1C0003: dout.push_back(rm[ 3]); //MCUPARAR3
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23'h1C0004: dout.push_back(rm[ 4]); //MCURESR0
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23'h1C0005: dout.push_back(rm[ 5]); //MCURESR1
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23'h1C0006: dout.push_back(rm[ 6]); //MCURESR2
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23'h1C0007: dout.push_back(rm[ 7]); //MCURESR3
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23'h1C0008: dout.push_back(32'b0) ;
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23'h1C0010: dout.push_back(rm[16]); //CWFR0
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23'h1C0011: dout.push_back(rm[17]); //CWFR1
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23'h1C0012: dout.push_back(rm[18]); //CWFR2
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23'h1C0013: dout.push_back(rm[19]); //CWFR3
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23'h1C0014: dout.push_back(rm[20]); //CWPRR
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23'h1C0015: dout.push_back(rm[21]); //GAPR0
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23'h1C0016: dout.push_back(rm[22]); //GAPR1
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23'h1C0017: dout.push_back(rm[23]); //GAPR2
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23'h1C0018: dout.push_back(rm[24]); //GAPR3
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23'h1C0019: dout.push_back(rm[25]); //GAPR4
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23'h1C001a: dout.push_back(rm[26]); //GAPR5
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23'h1C001b: dout.push_back(rm[27]); //GAPR6
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23'h1C001c: dout.push_back(rm[28]); //GAPR7
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23'h1C001d: dout.push_back(rm[29]); //LCPR
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23'h1C001e: dout.push_back(rm[30]); //AMPR0
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23'h1C001f: dout.push_back(rm[31]); //AMPR1
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23'h1C0020: dout.push_back(rm[32]); //AMPR2
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23'h1C0021: dout.push_back(rm[33]); //AMPR3
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23'h1C0022: dout.push_back(rm[34]); //BIASR0
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23'h1C0023: dout.push_back(rm[35]); //BIASR1
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23'h1C0024: dout.push_back(rm[36]); //BIASR2
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23'h1C0025: dout.push_back(rm[37]); //BIASR3
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23'h1C0026: dout.push_back(rm[38]); //RTIMR
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23'h1C0027: dout.push_back(rm[39]); //ICNTR
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23'h1C0028: dout.push_back(rm[40]); //FSIR
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23'h1C0029: dout.push_back(rm[41]); //INTPSELR
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23'h1C002a: dout.push_back(32'b0) ;
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endcase
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// $display("dout:%h",dout[$]);
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endtask: reg_read
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task mcu_refmodel::output_trace(bit[24:0] addr);
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mcureg_trans tr_temp;
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//delay caused by decoder
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@(posedge wif.clk);
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@(negedge wif.clk);
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tr_temp = new();
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if(addr[24:20] == 5'h7)
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begin
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tr_temp.mcu_result[0] = rm[ 4] ; //MCURESR0
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tr_temp.mcu_result[1] = rm[ 5] ; //MCURESR1
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tr_temp.mcu_result[2] = rm[ 6] ; //MCURESR2
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tr_temp.mcu_result[3] = rm[ 7] ; //MCURESR3
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tr_temp.mcu_cwfr[0] = rm[16] ; //CWFR0
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tr_temp.mcu_cwfr[1] = rm[17] ; //CWFR1
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tr_temp.mcu_cwfr[2] = rm[18] ; //CWFR2
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tr_temp.mcu_cwfr[3] = rm[19] ; //CWFR3
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tr_temp.mcu_nco_pha_clr = rm[20][0 : 0]; //CWPRR
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tr_temp.mcu_gapr[0] = rm[21][31:16]; //GAPR0
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tr_temp.mcu_gapr[1] = rm[22][31:16]; //GAPR1
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tr_temp.mcu_gapr[2] = rm[23][31:16]; //GAPR2
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tr_temp.mcu_gapr[3] = rm[24][31:16]; //GAPR3
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tr_temp.mcu_gapr[4] = rm[25][31:16]; //GAPR4
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tr_temp.mcu_gapr[5] = rm[26][31:16]; //GAPR5
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tr_temp.mcu_gapr[6] = rm[27][31:16]; //GAPR6
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tr_temp.mcu_gapr[7] = rm[28][31:16]; //GAPR7
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tr_temp.mcu_rz_pha = rm[29][15: 0]; //LCPR
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tr_temp.mcu_ampr[0] = rm[30][31:16]; //AMPR0
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tr_temp.mcu_ampr[1] = rm[31][31:16]; //AMPR1
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tr_temp.mcu_ampr[2] = rm[32][31:16]; //AMPR2
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tr_temp.mcu_ampr[3] = rm[33][31:16]; //AMPR3
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tr_temp.mcu_baisr[0] = rm[34][31:16]; //BIASR0
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tr_temp.mcu_baisr[1] = rm[35][31:16]; //BIASR1
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tr_temp.mcu_baisr[2] = rm[36][31:16]; //BIASR2
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tr_temp.mcu_baisr[3] = rm[37][31:16]; //BIASR3
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tr_temp.mcu_intp_sel = rm[38][1 : 0]; //INTPSELR
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mcuout.push_back(tr_temp);
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end
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//$display("addr:%0h",addr);
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//$display("rm:",rm);
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//$display("din:%h",din);
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endtask: output_trace
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