112 lines
4.8 KiB
Systemverilog
112 lines
4.8 KiB
Systemverilog
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class dacreg_trans;
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//input port
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rand bit Cal_end ;
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//output port
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rand bit Prbs ;
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rand bit [14 :0] Set0 ;
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rand bit [14 :0] Set1 ;
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rand bit [14 :0] Set2 ;
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rand bit [14 :0] Set3 ;
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rand bit [14 :0] Set4 ;
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rand bit [14 :0] Set5 ;
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rand bit [14 :0] Set6 ;
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rand bit [14 :0] Set7 ;
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rand bit [14 :0] Set8 ;
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rand bit [14 :0] Set9 ;
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rand bit [14 :0] Set10 ;
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rand bit [14 :0] Set11 ;
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rand bit [14 :0] Set12 ;
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rand bit [14 :0] Set13 ;
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rand bit [14 :0] Set14 ;
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rand bit [14 :0] Set15 ;
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rand bit [2 :0] Dac_addr ;
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rand bit [2 :0] Dac_dw ;
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rand bit [8 :0] Dac_ref ;
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rand bit [16 :0] Prbs_rst0 ;
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rand bit [16 :0] Prbs_set0 ;
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rand bit [16 :0] Prbs_rst1 ;
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rand bit [16 :0] Prbs_set1 ;
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rand bit Cal_sig ;
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rand bit Cal_rstn ;
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rand bit Cal_div_rstn;
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constraint cstr {
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Cal_end >= 0 ;
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Cal_end <= 5000 ;
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}
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function new();
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endfunction
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function bit[26:0] compare(dacreg_trans tr);
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bit[26:0] result = 27'b0;
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if(tr.Prbs != Prbs ) result[ 0]=1'b1;
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if(tr.Set0 != Set0 ) result[ 1]=1'b1;
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if(tr.Set1 != Set1 ) result[ 2]=1'b1;
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if(tr.Set2 != Set2 ) result[ 3]=1'b1;
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if(tr.Set3 != Set3 ) result[ 4]=1'b1;
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if(tr.Set4 != Set4 ) result[ 5]=1'b1;
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if(tr.Set5 != Set5 ) result[ 6]=1'b1;
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if(tr.Set6 != Set6 ) result[ 7]=1'b1;
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if(tr.Set7 != Set7 ) result[ 8]=1'b1;
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if(tr.Set8 != Set8 ) result[ 9]=1'b1;
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if(tr.Set9 != Set9 ) result[10]=1'b1;
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if(tr.Set10 != Set10 ) result[11]=1'b1;
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if(tr.Set11 != Set11 ) result[12]=1'b1;
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if(tr.Set12 != Set12 ) result[13]=1'b1;
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if(tr.Set13 != Set13 ) result[14]=1'b1;
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if(tr.Set14 != Set14 ) result[15]=1'b1;
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if(tr.Set15 != Set15 ) result[16]=1'b1;
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if(tr.Dac_addr != Dac_addr ) result[17]=1'b1;
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if(tr.Dac_dw != Dac_dw ) result[18]=1'b1;
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if(tr.Dac_ref != Dac_ref ) result[19]=1'b1;
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if(tr.Prbs_rst0 != Prbs_rst0 ) result[20]=1'b1;
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if(tr.Prbs_set0 != Prbs_set0 ) result[21]=1'b1;
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if(tr.Prbs_rst1 != Prbs_rst1 ) result[22]=1'b1;
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if(tr.Prbs_set1 != Prbs_set1 ) result[23]=1'b1;
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if(tr.Cal_sig != Cal_sig ) result[24]=1'b1;
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if(tr.Cal_rstn != Cal_rstn ) result[25]=1'b1;
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if(tr.Cal_div_rstn != Cal_div_rstn) result[26]=1'b1;
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return result;
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endfunction
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function print(bit[26:0] ctrl,integer fid);
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if(ctrl[ 0]) $fwrite(fid,"Prbs :\t%h\n", Prbs );
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if(ctrl[ 1]) $fwrite(fid,"Set0 :\t%h\n", Set0 );
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if(ctrl[ 2]) $fwrite(fid,"Set1 :\t%h\n", Set1 );
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if(ctrl[ 3]) $fwrite(fid,"Set2 :\t%h\n", Set2 );
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if(ctrl[ 4]) $fwrite(fid,"Set3 :\t%h\n", Set3 );
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if(ctrl[ 5]) $fwrite(fid,"Set4 :\t%h\n", Set4 );
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if(ctrl[ 6]) $fwrite(fid,"Set5 :\t%h\n", Set5 );
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if(ctrl[ 7]) $fwrite(fid,"Set6 :\t%h\n", Set6 );
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if(ctrl[ 8]) $fwrite(fid,"Set7 :\t%h\n", Set7 );
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if(ctrl[ 9]) $fwrite(fid,"Set8 :\t%h\n", Set8 );
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if(ctrl[10]) $fwrite(fid,"Set9 :\t%h\n", Set9 );
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if(ctrl[11]) $fwrite(fid,"Set10 :\t%h\n", Set10 );
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if(ctrl[12]) $fwrite(fid,"Set11 :\t%h\n", Set11 );
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if(ctrl[13]) $fwrite(fid,"Set12 :\t%h\n", Set12 );
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if(ctrl[14]) $fwrite(fid,"Set13 :\t%h\n", Set13 );
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if(ctrl[15]) $fwrite(fid,"Set14 :\t%h\n", Set14 );
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if(ctrl[16]) $fwrite(fid,"Set15 :\t%h\n", Set15 );
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if(ctrl[17]) $fwrite(fid,"Dac_addr :\t%h\n", Dac_addr );
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if(ctrl[18]) $fwrite(fid,"Dac_dw :\t%h\n", Dac_dw );
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if(ctrl[19]) $fwrite(fid,"Dac_ref :\t%h\n", Dac_ref );
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if(ctrl[20]) $fwrite(fid,"Prbs_rst0 :\t%h\n", Prbs_rst0 );
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if(ctrl[21]) $fwrite(fid,"Prbs_set0 :\t%h\n", Prbs_set0 );
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if(ctrl[22]) $fwrite(fid,"Prbs_rst1 :\t%h\n", Prbs_rst1 );
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if(ctrl[23]) $fwrite(fid,"Prbs_set1 :\t%h\n", Prbs_set1 );
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if(ctrl[24]) $fwrite(fid,"Cal_sig :\t%h\n", Cal_sig );
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if(ctrl[25]) $fwrite(fid,"Cal_rstn :\t%h\n", Cal_rstn );
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if(ctrl[26]) $fwrite(fid,"Cal_div_rstn:\t%h\n", Cal_div_rstn);
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endfunction
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endclass : dacreg_trans
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