18 lines
179 B
Systemverilog
18 lines
179 B
Systemverilog
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interface spi_if(input clk,input rstn);
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//timeunit 1ns;
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//timeprecision 1ps;
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logic sclk;
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logic csn;
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logic mosi;
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logic miso;
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endinterface : spi_if
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