1071 lines
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1071 lines
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|
"ksFw4",
|
||
|
|
"module",
|
||
|
|
30
|
||
|
|
],
|
||
|
|
"modout_mux": [
|
||
|
|
"modout_mux",
|
||
|
|
"jEu9i",
|
||
|
|
"module",
|
||
|
|
7
|
||
|
|
],
|
||
|
|
"spi_if": [
|
||
|
|
"spi_if",
|
||
|
|
"IHYdB",
|
||
|
|
"module",
|
||
|
|
42
|
||
|
|
],
|
||
|
|
"qbmcu_datalatch": [
|
||
|
|
"qbmcu_datalatch",
|
||
|
|
"MsCBG",
|
||
|
|
"module",
|
||
|
|
21
|
||
|
|
],
|
||
|
|
"sirv_gnrl_dffl": [
|
||
|
|
"sirv_gnrl_dffl",
|
||
|
|
"BM4bj",
|
||
|
|
"module",
|
||
|
|
8
|
||
|
|
],
|
||
|
|
"sram_if_0000": [
|
||
|
|
"sram_if_0000",
|
||
|
|
"nJgqZ",
|
||
|
|
"module",
|
||
|
|
4
|
||
|
|
],
|
||
|
|
"DAC_DEM_4": [
|
||
|
|
"DAC_DEM_4",
|
||
|
|
"WqW9L",
|
||
|
|
"module",
|
||
|
|
36
|
||
|
|
],
|
||
|
|
"tsdn28hpcpuhdb128x128m4mw_170a": [
|
||
|
|
"tsdn28hpcpuhdb128x128m4mw_170a",
|
||
|
|
"rShyv",
|
||
|
|
"module",
|
||
|
|
12
|
||
|
|
],
|
||
|
|
"ctrl_regfile": [
|
||
|
|
"ctrl_regfile",
|
||
|
|
"mLA3J",
|
||
|
|
"module",
|
||
|
|
5
|
||
|
|
],
|
||
|
|
"xyz_chip_top": [
|
||
|
|
"xyz_chip_top",
|
||
|
|
"VHUBa",
|
||
|
|
"module",
|
||
|
|
27
|
||
|
|
],
|
||
|
|
"param_lut_0002": [
|
||
|
|
"param_lut_0002",
|
||
|
|
"nJN5E",
|
||
|
|
"module",
|
||
|
|
6
|
||
|
|
],
|
||
|
|
"sirv_gnrl_ltch": [
|
||
|
|
"sirv_gnrl_ltch",
|
||
|
|
"UTi0b",
|
||
|
|
"module",
|
||
|
|
9
|
||
|
|
],
|
||
|
|
"PH2AMP": [
|
||
|
|
"PH2AMP",
|
||
|
|
"iYIEc",
|
||
|
|
"module",
|
||
|
|
17
|
||
|
|
],
|
||
|
|
"dacif": [
|
||
|
|
"dacif",
|
||
|
|
"SMgga",
|
||
|
|
"module",
|
||
|
|
28
|
||
|
|
],
|
||
|
|
"qbmcu_regfile_0000": [
|
||
|
|
"qbmcu_regfile_0000",
|
||
|
|
"Hit7c",
|
||
|
|
"module",
|
||
|
|
22
|
||
|
|
],
|
||
|
|
"dac_regfile": [
|
||
|
|
"dac_regfile",
|
||
|
|
"LR0zI",
|
||
|
|
"module",
|
||
|
|
10
|
||
|
|
],
|
||
|
|
"debug_top": [
|
||
|
|
"debug_top",
|
||
|
|
"gNaPt",
|
||
|
|
"module",
|
||
|
|
11
|
||
|
|
],
|
||
|
|
"mcu_regfile": [
|
||
|
|
"mcu_regfile",
|
||
|
|
"HWLgR",
|
||
|
|
"module",
|
||
|
|
18
|
||
|
|
],
|
||
|
|
"TB": [
|
||
|
|
"TB",
|
||
|
|
"sH4Fc",
|
||
|
|
"module",
|
||
|
|
37
|
||
|
|
],
|
||
|
|
"DUC_HB4": [
|
||
|
|
"DUC_HB4",
|
||
|
|
"zwWSN",
|
||
|
|
"module",
|
||
|
|
32
|
||
|
|
],
|
||
|
|
"thermo2binary_top": [
|
||
|
|
"thermo2binary_top",
|
||
|
|
"N7Gsb",
|
||
|
|
"module",
|
||
|
|
43
|
||
|
|
],
|
||
|
|
"qbmcu_busdecoder": [
|
||
|
|
"qbmcu_busdecoder",
|
||
|
|
"jAiwN",
|
||
|
|
"module",
|
||
|
|
19
|
||
|
|
],
|
||
|
|
"xy_dsp": [
|
||
|
|
"xy_dsp",
|
||
|
|
"U33JQ",
|
||
|
|
"module",
|
||
|
|
29
|
||
|
|
],
|
||
|
|
"qbmcu": [
|
||
|
|
"qbmcu",
|
||
|
|
"xnbfb",
|
||
|
|
"module",
|
||
|
|
20
|
||
|
|
],
|
||
|
|
"rst_gen_unit": [
|
||
|
|
"rst_gen_unit",
|
||
|
|
"anuMN",
|
||
|
|
"module",
|
||
|
|
23
|
||
|
|
],
|
||
|
|
"spi_slave": [
|
||
|
|
"spi_slave",
|
||
|
|
"eAsJz",
|
||
|
|
"module",
|
||
|
|
24
|
||
|
|
],
|
||
|
|
"system_regfile": [
|
||
|
|
"system_regfile",
|
||
|
|
"W3x1b",
|
||
|
|
"module",
|
||
|
|
25
|
||
|
|
],
|
||
|
|
"channel_top": [
|
||
|
|
"channel_top",
|
||
|
|
"xFWdC",
|
||
|
|
"module",
|
||
|
|
26
|
||
|
|
],
|
||
|
|
"DUC_HB3": [
|
||
|
|
"DUC_HB3",
|
||
|
|
"Rdd8k",
|
||
|
|
"module",
|
||
|
|
31
|
||
|
|
],
|
||
|
|
"DUC4": [
|
||
|
|
"DUC4",
|
||
|
|
"cwtAY",
|
||
|
|
"module",
|
||
|
|
33
|
||
|
|
],
|
||
|
|
"DAC_DEM": [
|
||
|
|
"DAC_DEM",
|
||
|
|
"brTVz",
|
||
|
|
"module",
|
||
|
|
34
|
||
|
|
],
|
||
|
|
"DAC_DEM_16": [
|
||
|
|
"DAC_DEM_16",
|
||
|
|
"gcyA4",
|
||
|
|
"module",
|
||
|
|
35
|
||
|
|
],
|
||
|
|
"DW_mult_pipe_0000_0000": [
|
||
|
|
"DW_mult_pipe_0000_0000",
|
||
|
|
"HNRiG",
|
||
|
|
"module",
|
||
|
|
38
|
||
|
|
],
|
||
|
|
"DW_mult_pipe_0000_0002": [
|
||
|
|
"DW_mult_pipe_0000_0002",
|
||
|
|
"SiiVi",
|
||
|
|
"module",
|
||
|
|
39
|
||
|
|
],
|
||
|
|
"DW01_addsub": [
|
||
|
|
"DW01_addsub",
|
||
|
|
"KysYq",
|
||
|
|
"module",
|
||
|
|
41
|
||
|
|
],
|
||
|
|
"...MASTER...": [
|
||
|
|
"SIM",
|
||
|
|
"amcQw",
|
||
|
|
"module",
|
||
|
|
44
|
||
|
|
]
|
||
|
|
},
|
||
|
|
"incremental": "on",
|
||
|
|
"LVLData": [
|
||
|
|
"SIM"
|
||
|
|
],
|
||
|
|
"Misc": {
|
||
|
|
"archive_dir": "archive.28",
|
||
|
|
"vcs_version": "O-2018.09-SP2_Full64",
|
||
|
|
"master_pid": 58486,
|
||
|
|
"vcs_build_date": "Build Date = Feb 28 2019 22:34:30",
|
||
|
|
"VCS_HOME": "/home/synopsys/vcs/O-2018.09-SP2",
|
||
|
|
"default_output_dir": "csrc",
|
||
|
|
"csrc_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/csrc",
|
||
|
|
"hostname": "IC_EDA",
|
||
|
|
"cwd": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top",
|
||
|
|
"csrc": "csrc",
|
||
|
|
"daidir": "simv.daidir",
|
||
|
|
"daidir_abs": "/home/ICer/ic_prjs/EZQ-XYZ-M1-V0.9/ezq-xyz-m1/sim/chip_top/simv.daidir"
|
||
|
|
},
|
||
|
|
"CurCompileUdps": {},
|
||
|
|
"CurCompileModules": [
|
||
|
|
"...MASTER...",
|
||
|
|
"_vcs_unit__3598111382",
|
||
|
|
"_vcs_unit__3598111382",
|
||
|
|
"std",
|
||
|
|
"sram_if",
|
||
|
|
"sram_if_0000",
|
||
|
|
"ctrl_regfile",
|
||
|
|
"param_lut_0002",
|
||
|
|
"modout_mux",
|
||
|
|
"sirv_gnrl_dffl",
|
||
|
|
"sirv_gnrl_ltch",
|
||
|
|
"dac_regfile",
|
||
|
|
"debug_top",
|
||
|
|
"tsdn28hpcpuhdb128x128m4mw_170a",
|
||
|
|
"tsdn28hpcpuhdb128x128m4mw_170a_Int_Array",
|
||
|
|
"tsdn28hpcpuhdb4096x32m4mw_170a",
|
||
|
|
"tsdn28hpcpuhdb4096x32m4mw_170a_Int_Array",
|
||
|
|
"tsdn28hpcpuhdb64x32m4mw_170a_Int_Array",
|
||
|
|
"PH2AMP",
|
||
|
|
"mcu_regfile",
|
||
|
|
"qbmcu_busdecoder",
|
||
|
|
"qbmcu",
|
||
|
|
"qbmcu_datalatch",
|
||
|
|
"qbmcu_regfile_0000",
|
||
|
|
"rst_gen_unit",
|
||
|
|
"spi_slave",
|
||
|
|
"spi_slave",
|
||
|
|
"system_regfile",
|
||
|
|
"channel_top",
|
||
|
|
"channel_top",
|
||
|
|
"xyz_chip_top",
|
||
|
|
"xyz_chip_top",
|
||
|
|
"dacif",
|
||
|
|
"dacif",
|
||
|
|
"xy_dsp",
|
||
|
|
"xy_dsp",
|
||
|
|
"DUC_HB2",
|
||
|
|
"DUC_HB2",
|
||
|
|
"DUC_HB3",
|
||
|
|
"DUC_HB3",
|
||
|
|
"DUC_HB4",
|
||
|
|
"DUC_HB4",
|
||
|
|
"DUC4",
|
||
|
|
"DUC4",
|
||
|
|
"DAC_DEM",
|
||
|
|
"DAC_DEM",
|
||
|
|
"DAC_DEM_16",
|
||
|
|
"DAC_DEM_16",
|
||
|
|
"DAC_DEM_4",
|
||
|
|
"DAC_DEM_4",
|
||
|
|
"TB",
|
||
|
|
"TB",
|
||
|
|
"DW_mult_pipe_0000_0000",
|
||
|
|
"DW_mult_pipe_0000_0002",
|
||
|
|
"DW01_addsub",
|
||
|
|
"spi_if",
|
||
|
|
"thermo2binary_top"
|
||
|
|
],
|
||
|
|
"rlimit": {
|
||
|
|
"data": -1,
|
||
|
|
"stack": -1
|
||
|
|
},
|
||
|
|
"CompileStatus": "Successful"
|
||
|
|
}
|