57 lines
1.4 KiB
Systemverilog
57 lines
1.4 KiB
Systemverilog
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class awgreg_monitor;
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virtual awgreg_if aif;
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virtual sram_if#(25,32) xif;
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//collect
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awgreg_trans act_trans[$];
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function new();
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endfunction
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extern task collect();
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extern task do_mon();
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endclass : awgreg_monitor
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task awgreg_monitor::do_mon();
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while(1) begin
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@(negedge xif.wren);
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collect();
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end
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endtask: do_mon
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task awgreg_monitor::collect();
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awgreg_trans tr_temp;
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@(posedge xif.clk);
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@(negedge xif.clk);
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tr_temp = new();
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tr_temp.mcu_param0 = aif.mcu_param0 ;
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tr_temp.mcu_param1 = aif.mcu_param1 ;
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tr_temp.mcu_param2 = aif.mcu_param2 ;
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tr_temp.mcu_param3 = aif.mcu_param3 ;
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tr_temp.fb_st_o = aif.fb_st_o ;
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tr_temp.mod_sel_sideband = aif.mod_sel_sideband;
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tr_temp.qam_nco_clr = aif.qam_nco_clr ;
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tr_temp.qam_nco_sclr_en = aif.qam_nco_sclr_en ;
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tr_temp.qam_fcw = aif.qam_fcw ;
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tr_temp.qam_pha = aif.qam_pha ;
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tr_temp.qam_mod = aif.qam_mod ;
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tr_temp.qam_sel_sideband = aif.qam_sel_sideband;
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tr_temp.intp_mode = aif.intp_mode ;
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tr_temp.role_sel = aif.role_sel ;
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tr_temp.dac_mode_sel = aif.dac_mode_sel ;
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tr_temp.dout_sel = aif.dout_sel ;
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act_trans.push_back(tr_temp);
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endtask: collect
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