SPI_Test/tb/awg_top/Makefile

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Makefile
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2024-06-25 16:41:01 +08:00
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all +define+DUMP_FSDB -lca -q -timescale=1ns/1ps +nospecify -P /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/novas_new_dumper.tab /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a -l compile.log
SIMV = ./simv -l sim.log
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sverilog -f files.f -top TB -nologo &
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~