SPI_Test/rtl/xy_dsp/duc/duc_hb4_top_s3.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    duc_hb4_top_s3.v
//  Department            :    
//  Author                :    
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.8         2024-03-26      thfu			modify delay
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module 	DUC_HB4_TOP_S3		(clkl,
				rstn,
				din0,
				din1,
                din2,
				din3,
				din4,
				din5,
                din6,
				din7,
				dout_p0,
				dout_p1,
				dout_p2,
				dout_p3,
				dout_p4,
				dout_p5,
				dout_p6,
				dout_p7,
				dout_p8,
				dout_p9,
				dout_pa,
				dout_pb,
				dout_pc,
				dout_pd,
				dout_pe,
				dout_pf
				);
input	clkl,rstn;

input	[15:0]	din0;
input	[15:0]	din1;
input	[15:0]	din2;
input	[15:0]	din3;
input	[15:0]	din4;
input	[15:0]	din5;
input	[15:0]	din6;
input	[15:0]	din7;

output	[15:0]	dout_p0;
output	[15:0]	dout_p1;
output	[15:0]	dout_p2;
output	[15:0]	dout_p3;
output	[15:0]	dout_p4;
output	[15:0]	dout_p5;
output	[15:0]	dout_p6;
output	[15:0]	dout_p7;
output	[15:0]	dout_p8;
output	[15:0]	dout_p9;
output	[15:0]	dout_pa;
output	[15:0]	dout_pb;
output	[15:0]	dout_pc;
output	[15:0]	dout_pd;
output	[15:0]	dout_pe;
output	[15:0]	dout_pf;

reg	[15:0]	din_r1;
reg	[15:0]	din_r2;
reg	[15:0]	din_r3;
reg	[15:0]	din_r4;
reg	[15:0]	din_r5;
reg	[15:0]	din_r6;
reg	[15:0]	din_r7;
reg	[15:0]	din_r8;
reg	[15:0]	din_r9;
reg	[15:0]	din_r10;
reg	[15:0]	din_r11;
reg	[15:0]	din_r12;
reg	[15:0]	din_r13;
reg	[15:0]	din_r14;
reg	[15:0]	din_r15;
reg	[15:0]	din_r16;
reg	[15:0]	din_r17;
reg	[15:0]	din_r18;
reg	[15:0]	din_r19;
reg	[15:0]	din_r20;
reg	[15:0]	din_r21;
reg	[15:0]	din_r22;
reg	[15:0]	din_r23;
reg	[15:0]	din_r24;
reg	[15:0]	din_r25;
reg	[15:0]	din_r26;
reg	[15:0]	din_r27;
reg	[15:0]	din_r28;
reg	[15:0]	din_r29;
reg	[15:0]	din_r30;
reg	[15:0]	din_r31;
reg	[15:0]	din_r32;
reg	[15:0]	din_r33;
reg	[15:0]	din_r34;
reg	[15:0]	din_r35;


always@(posedge clkl or negedge rstn)
	if(!rstn)
	begin
		din_r1	 <=	'b0;
		din_r2	 <=	'b0;
		din_r3	 <=	'b0;
		din_r4	 <=	'b0;
		din_r5	 <=	'b0;
		din_r6	 <=	'b0;
		din_r7	 <=	'b0;
		din_r8	 <=	'b0;
      	        din_r9	 <=	'b0;
		din_r10	 <=	'b0;
		din_r11	 <=	'b0;
		din_r12	 <=	'b0;
		din_r13	 <=	'b0;
		din_r14	 <=	'b0;
	end
	else
	begin
		din_r1	<=	din7;
		din_r2	<=	din6;
		din_r3	<=	din5;
		din_r4	<=	din4;
		din_r5	<=	din3;
		din_r6	<=	din2;
		din_r7	<=	din1;
		din_r8	<=	din0;

		din_r9	<=	din_r1;
		din_r17	<=	din_r9;
		din_r25	<=	din_r17;
		din_r33	<=	din_r25;


		din_r10	<=	din_r2;
		din_r18	<=	din_r10;
		din_r26	<=	din_r18;
		din_r34	<=	din_r26;

		din_r11	<=	din_r3;
		din_r19	<=	din_r11;
		din_r27	<=	din_r19;
		din_r35	<=	din_r27;

		din_r12	<=	din_r4;
		din_r20	<=	din_r12;
		din_r28	<=	din_r20;

		din_r13	<=	din_r5;
		din_r21	<=	din_r13;
		din_r29	<=	din_r21;

		din_r14	<=	din_r6;
		din_r22	<=	din_r14;
		din_r30	<=	din_r22;

		din_r15	<=	din_r7;
		din_r23	<=	din_r15;
		din_r31	<=	din_r23;

		din_r16	<=	din_r8;
		din_r24	<=	din_r16;
		din_r32	<=	din_r24;


	end




DUC_HB4	 	inst0_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din7),	
				.din_1		(din6),	
				.din_2		(din5),	 
				.din_3		(din4),	//dout_p0
				.din_4		(din3),
				.din_5		(din2),	
				.dout		(dout_p1)
		 	);


assign		dout_p0 =       din_r28;


DUC_HB4	 	inst1_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din6),	
				.din_1		(din5),	
				.din_2		(din4),	 
				.din_3		(din3),	//dout_p2
				.din_4		(din2),
				.din_5		(din1),	
				.dout		(dout_p3)
		 	);


assign		dout_p2 =       din_r29;		

DUC_HB4	 	inst2_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din5),	
				.din_1		(din4),	
				.din_2		(din3),	 
				.din_3		(din2),	//dout_p4
				.din_4		(din1),
				.din_5		(din0),	
				.dout		(dout_p5)
		 	);


assign		dout_p4 =       din_r30;		

DUC_HB4	 	inst3_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din4),	
				.din_1		(din3),	
				.din_2		(din2),	 
				.din_3		(din1),	//dout_p6
				.din_4		(din0),
				.din_5		(din_r1),	
				.dout		(dout_p7)
		 	);


assign		dout_p6 =       din_r31;	

DUC_HB4	 	inst4_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din3),	
				.din_1		(din2),	
				.din_2		(din1),	 
				.din_3		(din0),	//dout_p6
				.din_4		(din_r1),
				.din_5		(din_r2),	
				.dout		(dout_p9)
		 	);


assign		dout_p8 =       din_r32;

DUC_HB4	 	inst5_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din2),	
				.din_1		(din1),	
				.din_2		(din0),	 
				.din_3		(din_r1),	//dout_p6
				.din_4		(din_r2),
				.din_5		(din_r3),	
				.dout		(dout_pb)
		 	);


assign		dout_pa =       din_r33;	

DUC_HB4	 	inst6_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din1),	
				.din_1		(din0),	
				.din_2		(din_r1),	 
				.din_3		(din_r2),	//dout_p6
				.din_4		(din_r3),
				.din_5		(din_r4),	
				.dout		(dout_pd)
		 	);


assign		dout_pc =       din_r34;	

DUC_HB4	 	inst7_duc_hb4(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din0),	
				.din_1		(din_r1),	
				.din_2		(din_r2),	 
				.din_3		(din_r3),	//dout_p6
				.din_4		(din_r4),
				.din_5		(din_r5),	
				.dout		(dout_pf)
		 	);


assign		dout_pe =       din_r35;	
endmodule