SPI_Test/rtl/xy_dsp/duc/duc_hb3_pipe_shift.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    duc_hb3_shift.v
//  Department            :    
//  Author                :    
//  Author's Tel          :     
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//  Relese History
//  Version     Date            Author          Description
//  0.8         2024-03-26      thfu			output register
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//  Keywords            :       
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//  Parameter
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//  Purpose                 :
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module 	DUC_HB3	 	(
		 	clk,
		 	rstn,
		 	din_0,	
			din_1,	
			din_2,	 
			din_3,	
			din_4,
			din_5,	
			din_6,
			din_7,
			dout
		 	);		
input		clk;
input		rstn;
input	signed [15:0]	din_0;
input	signed [15:0]	din_1;
input	signed [15:0]	din_2;
input	signed [15:0]	din_3;
input	signed [15:0]	din_4;
input	signed [15:0]	din_5;
input	signed [15:0]	din_6;
input	signed [15:0]	din_7;

output	signed [15:0]	dout;

parameter	c0 	= 	-17'd210;
parameter	c1 	= 	 17'd1799;
parameter	c2	=	-17'd8234;
parameter	c3	=	 17'd39413;	

reg	signed [16:0]	sum_0_7;
reg	signed [16:0]	sum_1_6;
reg	signed [16:0]	sum_2_5;
reg	signed [16:0]	sum_3_4;


always@(posedge clk or negedge rstn)
		if(!rstn)	
			begin
				sum_0_7		<=	'h0;
				sum_1_6		<=	'h0;
				sum_2_5		<=	'h0;
				sum_3_4		<=	'h0;
			end
		else	
			begin
				sum_0_7		<=	{{1 {din_0[15]}},din_0} + {{1 {din_7[15]}},din_7};
				sum_1_6		<=	{{1 {din_1[15]}},din_1} + {{1 {din_6[15]}},din_6};
				sum_2_5		<=	{{1 {din_2[15]}},din_2} + {{1 {din_5[15]}},din_5};
				sum_3_4		<=	{{1 {din_3[15]}},din_3} + {{1 {din_4[15]}},din_4};
			end


wire	signed	[16:0]	mult_c0_sum0;
wire	signed	[19:0]	mult_c0_sum1;
wire	signed	[21:0]	mult_c0_sum2;
wire	signed	[22:0]	mult_c0_sum3;

assign	mult_c0_sum0 = sum_0_7; 	
assign	mult_c0_sum1 = {sum_0_7,3'b0}; 	
assign	mult_c0_sum2 = {sum_0_7,5'b0}; 	
assign	mult_c0_sum3 = {sum_0_7,6'b0}; 

reg	signed	[23:0]	mult_c0_sum;

always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c0_sum		<=	'h0;
		else	
			mult_c0_sum		<=	{{7{mult_c0_sum0[16]}},mult_c0_sum0} + {{4{mult_c0_sum1[19]}},mult_c0_sum1} + {{2{mult_c0_sum2[21]}},mult_c0_sum2} + {{1{mult_c0_sum3[22]}},mult_c0_sum3};


wire	signed	[18:0]	mult_c1_sum0;
wire	signed	[23:0]	mult_c1_sum1;
wire	signed	[26:0]	mult_c1_sum2;

assign	mult_c1_sum0 = {sum_1_6,2'b0}; 
assign	mult_c1_sum1 = {sum_1_6,7'b0}; 
assign	mult_c1_sum2 = {sum_1_6,10'b0}; 

reg	signed	[27:0]	mult_c1_sum;
always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c1_sum		<=	'h0;
		else	
			mult_c1_sum		<=	 {{9{mult_c1_sum0[18]}},mult_c1_sum0} - {{4{mult_c1_sum1[23]}},mult_c1_sum1} + {{1{mult_c1_sum2[26]}},mult_c1_sum2};


wire	signed	[16:0]	mult_c2_sum0;
wire	signed	[18:0]	mult_c2_sum1;
wire	signed	[20:0]	mult_c2_sum2;
wire	signed	[28:0]	mult_c2_sum3;

assign	mult_c2_sum0 = sum_2_5;
assign	mult_c2_sum1 = {sum_2_5,2'b0}; 	
assign	mult_c2_sum2 = {sum_2_5,4'b0}; 
assign	mult_c2_sum3 = {sum_2_5,12'b0}; 				

reg	signed	[29:0]	mult_c2_sum;

always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c2_sum		<=	'h0;
		else	
			mult_c2_sum		<=	{{13{mult_c2_sum0[16]}},mult_c2_sum0} + {{11{mult_c2_sum1[18]}},mult_c2_sum1} + {{9{mult_c2_sum2[20]}},mult_c2_sum2} + {{1{mult_c2_sum3[28]}},mult_c2_sum3};


wire	signed	[16:0]	mult_c3_sum0;
wire	signed	[17:0]	mult_c3_sum1;
wire	signed	[19:0]	mult_c3_sum2;
wire	signed	[24:0]	mult_c3_sum3;
wire	signed	[26:0]	mult_c3_sum4;
wire	signed	[27:0]	mult_c3_sum5;
wire	signed	[30:0]	mult_c3_sum6;
; 
assign	mult_c3_sum0 = sum_3_4; 
assign	mult_c3_sum1 = {sum_3_4,1'b0}; 
assign	mult_c3_sum2 = {sum_3_4,3'b0}; 
assign	mult_c3_sum3 = {sum_3_4,8'b0}; 
assign	mult_c3_sum4 = {sum_3_4,10'b0}; 
assign	mult_c3_sum5 = {sum_3_4,11'b0}; 
assign	mult_c3_sum6 = {sum_3_4,14'b0}; 

reg	signed	[31:0]	mult_c3_sum;

always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c3_sum		<=	'h0;
		else	
			mult_c3_sum		<=	 {{15{mult_c3_sum0[16]}},mult_c3_sum0} + {{14{mult_c3_sum1[17]}},mult_c3_sum1} - {{12{mult_c3_sum2[19]}},mult_c3_sum2} + {{7{mult_c3_sum3[24]}},mult_c3_sum3} + {{5{mult_c3_sum4[26]}},mult_c3_sum4} + {{4{mult_c3_sum5[27]}},mult_c3_sum5} + {{1{mult_c3_sum6[30]}},mult_c3_sum6};


reg	signed	[32:0]	mult_sum;

always@(posedge clk or negedge rstn) 
		if(!rstn)
			mult_sum		<=	'h0;
		else	
			mult_sum		<=	-{{9{mult_c0_sum[23]}},mult_c0_sum} + {{5{mult_c1_sum[27]}},mult_c1_sum} - {{3{mult_c2_sum[29]}},mult_c2_sum} + {{1{mult_c3_sum[31]}},mult_c3_sum};

wire signed [17:0]	dout0_w;

reg	signed [15:0]	dout0;

assign dout0_w = mult_sum[32:15]+mult_sum[14];

always@(posedge clk or negedge rstn)
	if(!rstn)
		dout0		<=	'h0;
	else if(dout0_w[16:15]==2'b01)
		dout0	<=	16'd32767;	
	else if(dout0_w[16:15]==2'b10)
		dout0	<=	-16'd32768;
	else
		dout0	<=	dout0_w[15:0];

assign	dout = dout0;

endmodule