SPI_Test/rtl/xy_dsp/duc/duc_hb1_pipe_shift.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    duc_hb1_shift.v
//  Department            :    
//  Author                :    
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.8         2024-03-26      thfu   add pipeline
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 : 
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
 
module  DUC_HB1   (
  clk,
  rstn,
  din_0, 
  din_1, 
  din_2,  
  din_3, 
  din_4,
  din_5, 
  din_6,
  din_7,
  din_8,
  din_9,
  din_10,
  din_11,
  din_12, 
  din_13, 
  din_14,  
  din_15, 
  din_16,
  din_17, 
  din_18,
  din_19,
  din_20,
  din_21,
  din_22,
  din_23,
  din_24, 
  din_25, 
  din_26,  
  din_27, 
  din_28,
  din_29, 
  din_30,
  din_31,
  din_32,
  din_33,
  din_34,
  din_35,
  dout
  );  
input        clk;
input        rstn;
input signed [15:0] din_0;
input signed [15:0] din_1;
input signed [15:0] din_2;
input signed [15:0] din_3;
input signed [15:0] din_4;
input signed [15:0] din_5;
input signed [15:0] din_6;
input signed [15:0] din_7;
input signed [15:0] din_8;
input signed [15:0] din_9;
input signed [15:0] din_10;
input signed [15:0] din_11;
input signed [15:0] din_12;
input signed [15:0] din_13;
input signed [15:0] din_14;
input signed [15:0] din_15;
input signed [15:0] din_16;
input signed [15:0] din_17;
input signed [15:0] din_18;
input signed [15:0] din_19;
input signed [15:0] din_20;
input signed [15:0] din_21;
input signed [15:0] din_22;
input signed [15:0] din_23;
input signed [15:0] din_24;
input signed [15:0] din_25;
input signed [15:0] din_26;
input signed [15:0] din_27;
input signed [15:0] din_28;
input signed [15:0] din_29;
input signed [15:0] din_30;
input signed [15:0] din_31;
input signed [15:0] din_32;
input signed [15:0] din_33;
input signed [15:0] din_34;
input signed [15:0] din_35;


output signed [15:0] dout;

parameter c0  = -20'd28;
parameter c1  =  20'd82;
parameter c2  = -20'd194;
parameter c3  =  20'd397;
parameter c4  = -20'd737;
parameter c5  =  20'd1275;
parameter c6  = -20'd2084;
parameter c7  =  20'd3258;
parameter c8  = -20'd4910;
parameter c9  =  20'd7184;
parameter c10 = -20'd10274;
parameter c11 =  20'd14457;
parameter c12 = -20'd20187;
parameter c13 =  20'd28286;
parameter c14 = -20'd40513;
parameter c15 =  20'd61451;
parameter c16 = -20'd108000;
parameter c17 =  20'd332673;

reg signed [16:0] sum_0_35;
reg signed [16:0] sum_1_34;
reg signed [16:0] sum_2_33;
reg signed [16:0] sum_3_32;
reg signed [16:0] sum_4_31;
reg signed [16:0] sum_5_30;
reg signed [16:0] sum_6_29;
reg signed [16:0] sum_7_28;
reg signed [16:0] sum_8_27;
reg signed [16:0] sum_9_26;
reg signed [16:0] sum_10_25;
reg signed [16:0] sum_11_24;
reg signed [16:0] sum_12_23;
reg signed [16:0] sum_13_22;
reg signed [16:0] sum_14_21;
reg signed [16:0] sum_15_20;
reg signed [16:0] sum_16_19;
reg signed [16:0] sum_17_18;

always@(posedge clk or negedge rstn) begin
  if(!rstn) begin
    sum_0_35 <= 'h0;
    sum_1_34 <= 'h0;
    sum_2_33 <= 'h0;
    sum_3_32 <= 'h0;
    sum_4_31 <= 'h0;
    sum_5_30 <= 'h0;
    sum_6_29 <= 'h0;
    sum_7_28 <= 'h0;
    sum_8_27 <= 'h0;
    sum_9_26 <= 'h0;
    sum_10_25 <= 'h0;
    sum_11_24 <= 'h0;
    sum_12_23 <= 'h0;
    sum_13_22 <= 'h0;
    sum_14_21 <= 'h0;
    sum_15_20 <= 'h0;
    sum_16_19 <= 'h0;
    sum_17_18 <= 'h0;
  end
  else begin
    sum_0_35 <= {{1 {din_0[15]}},din_0} + {{1 {din_35[15]}},din_35};
    sum_1_34 <= {{1 {din_1[15]}},din_1} + {{1 {din_34[15]}},din_34};
    sum_2_33 <= {{1 {din_2[15]}},din_2} + {{1 {din_33[15]}},din_33};
    sum_3_32 <= {{1 {din_3[15]}},din_3} + {{1 {din_32[15]}},din_32};
    sum_4_31 <= {{1 {din_4[15]}},din_4} + {{1 {din_31[15]}},din_31};
    sum_5_30 <= {{1 {din_5[15]}},din_5} + {{1 {din_30[15]}},din_30};
    sum_6_29 <= {{1 {din_6[15]}},din_6} + {{1 {din_29[15]}},din_29};
    sum_7_28 <= {{1 {din_7[15]}},din_7} + {{1 {din_28[15]}},din_28};
    sum_8_27 <= {{1 {din_8[15]}},din_8} + {{1 {din_27[15]}},din_27};
    sum_9_26 <= {{1 {din_9[15]}},din_9} + {{1 {din_26[15]}},din_26};
    sum_10_25 <= {{1 {din_10[15]}},din_10} + {{1 {din_25[15]}},din_25};
    sum_11_24 <= {{1 {din_11[15]}},din_11} + {{1 {din_24[15]}},din_24};
    sum_12_23 <= {{1 {din_12[15]}},din_12} + {{1 {din_23[15]}},din_23};
    sum_13_22 <= {{1 {din_13[15]}},din_13} + {{1 {din_22[15]}},din_22};
    sum_14_21 <= {{1 {din_14[15]}},din_14} + {{1 {din_21[15]}},din_21};
    sum_15_20 <= {{1 {din_15[15]}},din_15} + {{1 {din_20[15]}},din_20};
    sum_16_19 <= {{1 {din_16[15]}},din_16} + {{1 {din_19[15]}},din_19};
    sum_17_18 <= {{1 {din_17[15]}},din_17} + {{1 {din_18[15]}},din_18};
  end
end

wire signed [17:0] mult_c0_sum0;

assign mult_c0_sum0 = {sum_0_35,1'b0}; 

reg  signed [17:0] mult_c0_sum;

always@(posedge clk or negedge rstn) begin
  if(!rstn)
    mult_c0_sum  <= 'h0;
  else 
    mult_c0_sum  <= mult_c0_sum0;
end

wire signed [16:0] mult_c1_sum0;
wire signed [18:0] mult_c1_sum1;

assign mult_c1_sum0 = sum_1_34; 
assign mult_c1_sum1 = {sum_1_34,2'b0};

reg  signed [19:0] mult_c1_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c1_sum  <= 'h0;
  else 
   mult_c1_sum  <=  {{3{mult_c1_sum0[16]}},mult_c1_sum0} + {{1{mult_c1_sum1[18]}},mult_c1_sum1};


wire signed [18:0] mult_c2_sum0;
wire signed [19:0] mult_c2_sum1;

assign mult_c2_sum0 = {sum_2_33,2'b0};
assign mult_c2_sum1 = {sum_2_33,3'b0};

reg signed [20:0] mult_c2_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c2_sum  <= 'h0;
  else 
   mult_c2_sum  <=  {{2{mult_c2_sum0[18]}},mult_c2_sum0} + {{1{mult_c2_sum1[19]}},mult_c2_sum1};


wire signed [16:0] mult_c3_sum0;
wire signed [19:0] mult_c3_sum1;
wire signed [20:0] mult_c3_sum2;

assign mult_c3_sum0 = sum_3_32; 
assign mult_c3_sum1 = {sum_3_32,3'b0}; 
assign mult_c3_sum2 = {sum_3_32,4'b0}; 

reg signed [21:0] mult_c3_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c3_sum  <= 'h0;
  else 
   mult_c3_sum  <=  {{5{mult_c3_sum0[16]}},mult_c3_sum0} + {{2{mult_c3_sum1[19]}},mult_c3_sum1} + {{1{mult_c3_sum2[20]}},mult_c3_sum2};



wire signed [17:0] mult_c4_sum0;
wire signed [20:0] mult_c4_sum1;
wire signed [21:0] mult_c4_sum2;

assign mult_c4_sum0 = {sum_4_31,1'b0}; 
assign mult_c4_sum1 = {sum_4_31,4'b0}; 
assign mult_c4_sum2 = {sum_4_31,5'b0}; 

reg signed [22:0] mult_c4_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c4_sum  <= 'h0;
  else 
   mult_c4_sum  <= - {{5{mult_c4_sum0[17]}},mult_c4_sum0} + {{2{mult_c4_sum1[20]}},mult_c4_sum1} + {{1{mult_c4_sum2[21]}},mult_c4_sum2};



wire signed [20:0] mult_c5_sum0;
wire signed [21:0] mult_c5_sum1;
wire signed [23:0] mult_c5_sum2;
 
assign mult_c5_sum0 = {sum_5_30,4'b0}; 
assign mult_c5_sum1 = {sum_5_30,5'b0}; 
assign mult_c5_sum2 = {sum_5_30,7'b0}; 

reg signed [24:0] mult_c5_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c5_sum  <= 'h0;
  else 
   mult_c5_sum  <= -{{4{mult_c5_sum0[20]}},mult_c5_sum0} - {{3{mult_c5_sum1[21]}},mult_c5_sum1} + {{1{mult_c5_sum2[23]}},mult_c5_sum2};




wire signed [17:0] mult_c6_sum0;
wire signed [23:0] mult_c6_sum1;
 
assign mult_c6_sum0 = {sum_6_29,1'b0};
assign mult_c6_sum1 = {sum_6_29,7'b0}; 

reg signed [24:0] mult_c6_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c6_sum  <= 'h0;
  else 
   mult_c6_sum  <=  {{7{mult_c6_sum0[17]}},mult_c6_sum0} + {{1{mult_c6_sum1[23]}},mult_c6_sum1};



wire signed [18:0] mult_c7_sum0;
wire signed [20:0] mult_c7_sum1;
wire signed [21:0] mult_c7_sum2;
wire signed [24:0] mult_c7_sum3;

assign mult_c7_sum0 = {sum_7_28,2'b0}; 
assign mult_c7_sum1 = {sum_7_28,4'b0}; 
assign mult_c7_sum2 = {sum_7_28,5'b0}; 
assign mult_c7_sum3 = {sum_7_28,8'b0}; 

reg signed [25:0]  mult_c7_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c7_sum  <= 'h0;
  else 
   mult_c7_sum  <= -{{7{mult_c7_sum0[18]}},mult_c7_sum0} - {{5{mult_c7_sum1[20]}},mult_c7_sum1} - {{4{mult_c7_sum2[21]}},mult_c7_sum2} + {{1{mult_c7_sum3[24]}},mult_c7_sum3};



wire signed [16:0] mult_c8_sum0;
wire signed [17:0] mult_c8_sum1;
wire signed [20:0] mult_c8_sum2;
wire signed [21:0] mult_c8_sum3;
wire signed [24:0] mult_c8_sum4;
 
assign mult_c8_sum0 = sum_8_27; 
assign mult_c8_sum1 = {sum_8_27,1'b0}; 
assign mult_c8_sum2 = {sum_8_27,4'b0}; 
assign mult_c8_sum3 = {sum_8_27,5'b0}; 
assign mult_c8_sum4 = {sum_8_27,8'b0}; 

reg  signed [25:0] mult_c8_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c8_sum  <= 'h0;
  else 
   mult_c8_sum  <=   {{9{mult_c8_sum0[16]}},mult_c8_sum0} + {{8{mult_c8_sum1[17]}},mult_c8_sum1} + {{5{mult_c8_sum2[20]}},mult_c8_sum2} + {{4{mult_c8_sum3[21]}},mult_c8_sum3} + {{1{mult_c8_sum4[24]}},mult_c8_sum4};



wire signed [16:0] mult_c9_sum0;
wire signed [22:0] mult_c9_sum1;
wire signed [25:0] mult_c9_sum2;

assign mult_c9_sum0 = sum_9_26; 
assign mult_c9_sum1 = {sum_9_26,6'b0}; 
assign mult_c9_sum2 = {sum_9_26,9'b0}; 

reg  signed [26:0]   mult_c9_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c9_sum  <= 'h0;
  else 
   mult_c9_sum  <= {{10{mult_c9_sum0[16]}},mult_c9_sum0} - {{4{mult_c9_sum1[22]}},mult_c9_sum1} + {{1{mult_c9_sum2[25]}},mult_c9_sum2};




wire signed [17:0] mult_c10_sum0;
wire signed [23:0] mult_c10_sum1;
wire signed [25:0] mult_c10_sum2;

assign mult_c10_sum0 = {sum_10_25,1'b0}; 
assign mult_c10_sum1 = {sum_10_25,7'b0}; 
assign mult_c10_sum2 = {sum_10_25,9'b0}; 

reg signed [26:0] mult_c10_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c10_sum  <= 'h0;
  else 
   mult_c10_sum  <=  {{9{mult_c10_sum0[17]}},mult_c10_sum0} + {{3{mult_c10_sum1[23]}},mult_c10_sum1} + {{1{mult_c10_sum2[25]}},mult_c10_sum2};



wire signed [19:0] mult_c11_sum0;
wire signed [23:0] mult_c11_sum1;
wire signed [26:0] mult_c11_sum2;

assign mult_c11_sum0 = {sum_11_24,3'b0}; 
assign mult_c11_sum1 = {sum_11_24,7'b0}; 
assign mult_c11_sum2 = {sum_11_24,10'b0}; 

reg signed [27:0]  mult_c11_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c11_sum  <= 'h0;
  else 
   mult_c11_sum  <= {{8{mult_c11_sum0[19]}},mult_c11_sum0} - {{4{mult_c11_sum1[23]}},mult_c11_sum1} + {{1{mult_c11_sum2[26]}},mult_c11_sum2};



wire signed [17:0] mult_c12_sum0;
wire signed [20:0] mult_c12_sum1;
wire signed [24:0] mult_c12_sum2;
wire signed [25:0] mult_c12_sum3;
wire signed [27:0] mult_c12_sum4;

assign mult_c12_sum0 = {sum_12_23,1'b0}; 
assign mult_c12_sum1 = {sum_12_23,4'b0}; 
assign mult_c12_sum2 = {sum_12_23,8'b0}; 
assign mult_c12_sum3 = {sum_12_23,9'b0}; 
assign mult_c12_sum4 = {sum_12_23,11'b0}; 

reg signed [28:0]  mult_c12_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c12_sum  <= 'h0;
  else 
   mult_c12_sum  <=  - {{11{mult_c12_sum0[17]}},mult_c12_sum0} - {{8{mult_c12_sum1[20]}},mult_c12_sum1} - {{4{mult_c12_sum2[24]}},mult_c12_sum2} - {{3{mult_c12_sum3[25]}},mult_c12_sum3} + {{1{mult_c12_sum4[27]}},mult_c12_sum4};



wire signed [19:0] mult_c13_sum0;
wire signed [20:0] mult_c13_sum1;
wire signed [24:0] mult_c13_sum2;
wire signed [27:0] mult_c13_sum3;

assign mult_c13_sum0 = {sum_13_22,3'b0}; 
assign mult_c13_sum1 = {sum_13_22,4'b0}; 
assign mult_c13_sum2 = {sum_13_22,8'b0}; 
assign mult_c13_sum3 = {sum_13_22,11'b0}; 

reg signed [28:0] mult_c13_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c13_sum  <= 'h0;
  else 
   mult_c13_sum  <=  - {{9{mult_c13_sum0[19]}},mult_c13_sum0} - {{8{mult_c13_sum1[20]}},mult_c13_sum1} - {{4{mult_c13_sum2[24]}},mult_c13_sum2} + {{1{mult_c13_sum3[27]}},mult_c13_sum3};



wire signed [18:0] mult_c14_sum0;
wire signed [21:0] mult_c14_sum1;
wire signed [25:0] mult_c14_sum2;
wire signed [27:0] mult_c14_sum3;

assign mult_c14_sum0 = {sum_14_21,2'b0}; 
assign mult_c14_sum1 = {sum_14_21,5'b0}; 
assign mult_c14_sum2 = {sum_14_21,9'b0}; 
assign mult_c14_sum3 = {sum_14_21,11'b0};

reg signed [28:0] mult_c14_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c14_sum  <= 'h0;
  else 
   mult_c14_sum  <=  {{10{mult_c14_sum0[18]}},mult_c14_sum0} - {{7{mult_c14_sum1[21]}},mult_c14_sum1} + {{3{mult_c14_sum2[25]}},mult_c14_sum2} + {{1{mult_c14_sum3[27]}},mult_c14_sum3};



wire signed [16:0] mult_c15_sum0;
wire signed [24:0] mult_c15_sum1;
wire signed [28:0] mult_c15_sum2;

assign mult_c15_sum0 = sum_15_20; 
assign mult_c15_sum1 = {sum_15_20,8'b0}; 
assign mult_c15_sum2 = {sum_15_20,12'b0}; 

reg signed [29:0]  mult_c15_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c15_sum  <= 'h0;
  else 
   mult_c15_sum  <=  {{13{mult_c15_sum0[16]}},mult_c15_sum0} - {{5{mult_c15_sum1[24]}},mult_c15_sum1} + {{1{mult_c15_sum2[28]}},mult_c15_sum2};



wire signed [17:0] mult_c16_sum0;
wire signed [21:0] mult_c16_sum1;
wire signed [22:0] mult_c16_sum2;
wire signed [25:0] mult_c16_sum3;
wire signed [27:0] mult_c16_sum4;
wire signed [28:0] mult_c16_sum5;

assign mult_c16_sum0 = {sum_16_19,1'b0}; 
assign mult_c16_sum1 = {sum_16_19,5'b0}; 
assign mult_c16_sum2 = {sum_16_19,6'b0}; 
assign mult_c16_sum3 = {sum_16_19,9'b0}; 
assign mult_c16_sum4 = {sum_16_19,11'b0}; 
assign mult_c16_sum5 = {sum_16_19,12'b0}; 

reg signed [29:0] mult_c16_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c16_sum  <= 'h0;
  else 
   mult_c16_sum  <= -{{12{mult_c16_sum0[17]}},mult_c16_sum0} + {{8{mult_c16_sum1[21]}},mult_c16_sum1} + {{7{mult_c16_sum2[22]}},mult_c16_sum2} + {{4{mult_c16_sum3[25]}},mult_c16_sum3} + {{2{mult_c16_sum4[27]}},mult_c16_sum4} + {{1{mult_c16_sum5[28]}},mult_c16_sum5};



wire signed [19:0] mult_c17_sum0;
wire signed [22:0] mult_c17_sum1;
wire signed [24:0] mult_c17_sum2;
wire signed [28:0] mult_c17_sum3;
wire signed [30:0] mult_c17_sum4;

assign mult_c17_sum0 = {sum_17_18,3'b0}; 
assign mult_c17_sum1 = {sum_17_18,6'b0}; 
assign mult_c17_sum2 = {sum_17_18,8'b0}; 
assign mult_c17_sum3 = {sum_17_18,12'b0}; 
assign mult_c17_sum4 = {sum_17_18,14'b0}; 

reg signed [31:0] mult_c17_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_c17_sum  <= 'h0;
  else 
   mult_c17_sum  <=  - {{12{mult_c17_sum0[19]}},mult_c17_sum0} + {{9{mult_c17_sum1[22]}},mult_c17_sum1} + {{7{mult_c17_sum2[24]}},mult_c17_sum2} + {{3{mult_c17_sum3[28]}},mult_c17_sum3} + {{1{mult_c17_sum4[30]}},mult_c17_sum4};
       


reg signed [22:0] mult_sum_r1;
reg signed [27:0] mult_sum_r2;
reg signed [30:0] mult_sum_r3;
reg signed [32:0] mult_sum_r4; 

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_sum_r1  <= 'h0;
  else 
   mult_sum_r1  <=  -{{5{mult_c0_sum[17]}},mult_c0_sum} + {{3{mult_c1_sum[19]}},mult_c1_sum} - {{2{mult_c2_sum[20]}},mult_c2_sum} + {{1{mult_c3_sum[21]}},mult_c3_sum};

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_sum_r2  <= 'h0;
  else 
   mult_sum_r2  <=  -{{5{mult_c4_sum[22]}},mult_c4_sum} + {{3{mult_c5_sum[24]}},mult_c5_sum} - {{3{mult_c6_sum[24]}},mult_c6_sum} + {{2{mult_c7_sum[25]}},mult_c7_sum};

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_sum_r3  <= 'h0;
  else 
   mult_sum_r3  <=  -{{5{mult_c8_sum[25]}},mult_c8_sum} + {{4{mult_c9_sum[26]}},mult_c9_sum} - {{4{mult_c10_sum[26]}},mult_c10_sum} + {{3{mult_c11_sum[27]}},mult_c11_sum} - {{2{mult_c12_sum[28]}},mult_c12_sum};

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_sum_r4  <= 'h0;
  else 
   mult_sum_r4  <=  {{4{mult_c13_sum[28]}},mult_c13_sum} - {{4{mult_c14_sum[28]}},mult_c14_sum} + {{3{mult_c15_sum[29]}},mult_c15_sum} - {{3{mult_c16_sum[29]}},mult_c16_sum} + {{1{mult_c17_sum[31]}},mult_c17_sum};

reg signed [33:0] mult_sum;

always@(posedge clk or negedge rstn)
  if(!rstn)
   mult_sum  <= 'h0;
  else 
   mult_sum  <=  mult_sum_r1 + mult_sum_r2 + mult_sum_r3 + mult_sum_r4;
   
   
reg signed [15:0] dout0;

wire  [19:0]  dout0_w;

assign dout0_w = mult_sum[33:15] + mult_sum[14];

always@(posedge clk or negedge rstn)
  if(!rstn)
   dout0  <= 'h0;
  else if(dout0_w[16:15]==2'b01)
   dout0 <= 16'd32767; 
  else if(dout0_w[16:15]==2'b10)
   dout0 <= -16'd32768;
  else
   dout0 <= dout0_w[15:0];

assign dout = dout0;


endmodule