273 lines
8.4 KiB
Coq
273 lines
8.4 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : dsp_top.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.4 2024-03-12 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module dsp_top (
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input clk
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,input rstn
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,input phase_manual_clr
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,input phase_auto_clr
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,input [47:0] fcw
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,input [15:0] pha
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,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
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//2'b10:cos;2'b11:sin;
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,input sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
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,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
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//3'b011:x8;3'b100:x16;
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,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
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//2'b10:2xNRZ mode;2'b00:reserve;
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,input [15:0] din_i
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,input [15:0] din_q
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//data output
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,output [15:0] dout0
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,output [15:0] dout1
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,output [15:0] dout2
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,output [15:0] dout3
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,output [15:0] dout4
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,output [15:0] dout5
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,output [15:0] dout6
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,output [15:0] dout7
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,output [15:0] dout8
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,output [15:0] dout9
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,output [15:0] dout10
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,output [15:0] dout11
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,output [15:0] dout12
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,output [15:0] dout13
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,output [15:0] dout14
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,output [15:0] dout15
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);
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wire [15:0] dt_i_0;
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wire [15:0] dt_i_1;
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wire [15:0] dt_i_2;
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wire [15:0] dt_i_3;
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wire [15:0] dt_i_4;
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wire [15:0] dt_i_5;
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wire [15:0] dt_i_6;
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wire [15:0] dt_i_7;
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wire [15:0] dt_i_8;
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wire [15:0] dt_i_9;
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wire [15:0] dt_i_a;
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wire [15:0] dt_i_b;
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wire [15:0] dt_i_c;
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wire [15:0] dt_i_d;
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wire [15:0] dt_i_e;
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wire [15:0] dt_i_f;
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wire [15:0] dt_q_0;
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wire [15:0] dt_q_1;
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wire [15:0] dt_q_2;
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wire [15:0] dt_q_3;
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wire [15:0] dt_q_4;
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wire [15:0] dt_q_5;
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wire [15:0] dt_q_6;
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wire [15:0] dt_q_7;
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wire [15:0] dt_q_8;
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wire [15:0] dt_q_9;
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wire [15:0] dt_q_a;
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wire [15:0] dt_q_b;
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wire [15:0] dt_q_c;
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wire [15:0] dt_q_d;
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wire [15:0] dt_q_e;
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wire [15:0] dt_q_f;
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DUC4 inst_duc_top_i (
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.clkl ( clk )
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,.rstn ( rstn )
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,.intp_mode ( intp_mode )
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,.din ( din_i )
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,.dout_p0 ( dt_i_0 )
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,.dout_p1 ( dt_i_1 )
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,.dout_p2 ( dt_i_2 )
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,.dout_p3 ( dt_i_3 )
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,.dout_p4 ( dt_i_4 )
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,.dout_p5 ( dt_i_5 )
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,.dout_p6 ( dt_i_6 )
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,.dout_p7 ( dt_i_7 )
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,.dout_p8 ( dt_i_8 )
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,.dout_p9 ( dt_i_9 )
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,.dout_pa ( dt_i_a )
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,.dout_pb ( dt_i_b )
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,.dout_pc ( dt_i_c )
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,.dout_pd ( dt_i_d )
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,.dout_pe ( dt_i_e )
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,.dout_pf ( dt_i_f )
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);
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DUC4 inst_duc_top_q (
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.clkl ( clk )
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,.rstn ( rstn )
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,.intp_mode ( intp_mode )
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,.din ( din_q )
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,.dout_p0 ( dt_q_0 )
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,.dout_p1 ( dt_q_1 )
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,.dout_p2 ( dt_q_2 )
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,.dout_p3 ( dt_q_3 )
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,.dout_p4 ( dt_q_4 )
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,.dout_p5 ( dt_q_5 )
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,.dout_p6 ( dt_q_6 )
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,.dout_p7 ( dt_q_7 )
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,.dout_p8 ( dt_q_8 )
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,.dout_p9 ( dt_q_9 )
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,.dout_pa ( dt_q_a )
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,.dout_pb ( dt_q_b )
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,.dout_pc ( dt_q_c )
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,.dout_pd ( dt_q_d )
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,.dout_pe ( dt_q_e )
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,.dout_pf ( dt_q_f )
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);
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wire [15:0] qam_0;
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wire [15:0] qam_1;
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wire [15:0] qam_2;
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wire [15:0] qam_3;
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wire [15:0] qam_4;
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wire [15:0] qam_5;
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wire [15:0] qam_6;
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wire [15:0] qam_7;
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wire [15:0] qam_8;
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wire [15:0] qam_9;
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wire [15:0] qam_a;
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wire [15:0] qam_b;
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wire [15:0] qam_c;
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wire [15:0] qam_d;
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wire [15:0] qam_e;
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wire [15:0] qam_f;
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QAM_TOP inst_qam_top (
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.clk ( clk )
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,.rstn ( rstn )
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,.phase_manual_clr ( phase_manual_clr )
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,.phase_auto_clr ( phase_auto_clr )
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,.fcw ( fcw )
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,.pha ( pha )
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,.qam_mod ( qam_mod )
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,.sel_sideband ( sel_sideband )
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,.din_i_0 ( dt_i_0 )
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,.din_i_1 ( dt_i_1 )
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,.din_i_2 ( dt_i_2 )
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,.din_i_3 ( dt_i_3 )
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,.din_i_4 ( dt_i_4 )
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,.din_i_5 ( dt_i_5 )
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,.din_i_6 ( dt_i_6 )
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,.din_i_7 ( dt_i_7 )
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,.din_i_8 ( dt_i_8 )
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,.din_i_9 ( dt_i_9 )
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,.din_i_10 ( dt_i_a )
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,.din_i_11 ( dt_i_b )
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,.din_i_12 ( dt_i_c )
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,.din_i_13 ( dt_i_d )
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,.din_i_14 ( dt_i_e )
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,.din_i_15 ( dt_i_f )
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,.din_q_0 ( dt_q_0 )
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,.din_q_1 ( dt_q_1 )
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,.din_q_2 ( dt_q_2 )
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,.din_q_3 ( dt_q_3 )
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,.din_q_4 ( dt_q_4 )
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,.din_q_5 ( dt_q_5 )
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,.din_q_6 ( dt_q_6 )
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,.din_q_7 ( dt_q_7 )
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,.din_q_8 ( dt_q_8 )
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,.din_q_9 ( dt_q_9 )
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,.din_q_10 ( dt_q_a )
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,.din_q_11 ( dt_q_b )
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,.din_q_12 ( dt_q_c )
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,.din_q_13 ( dt_q_d )
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,.din_q_14 ( dt_q_e )
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,.din_q_15 ( dt_q_f )
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,.dout_i_0 ( qam_0 )
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,.dout_i_1 ( qam_1 )
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,.dout_i_2 ( qam_2 )
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,.dout_i_3 ( qam_3 )
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,.dout_i_4 ( qam_4 )
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,.dout_i_5 ( qam_5 )
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,.dout_i_6 ( qam_6 )
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,.dout_i_7 ( qam_7 )
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,.dout_i_8 ( qam_8 )
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,.dout_i_9 ( qam_9 )
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,.dout_i_10 ( qam_a )
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,.dout_i_11 ( qam_b )
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,.dout_i_12 ( qam_c )
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,.dout_i_13 ( qam_d )
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,.dout_i_14 ( qam_e )
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,.dout_i_15 ( qam_f )
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);
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dacif dacif_inst (
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.clk ( clk )
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,.rstn ( rstn )
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,.dac_mode_sel ( dac_mode_sel )
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,.intp_mode ( intp_mode )
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,.din0 ( qam_0 )
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,.din1 ( qam_1 )
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,.din2 ( qam_2 )
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,.din3 ( qam_3 )
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,.din4 ( qam_4 )
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,.din5 ( qam_5 )
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,.din6 ( qam_6 )
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,.din7 ( qam_7 )
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,.din8 ( qam_8 )
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,.din9 ( qam_9 )
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,.din10 ( qam_a )
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,.din11 ( qam_b )
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,.din12 ( qam_c )
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,.din13 ( qam_d )
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,.din14 ( qam_e )
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,.din15 ( qam_f )
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,.dout0 ( dout0 )
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,.dout1 ( dout1 )
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,.dout2 ( dout2 )
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,.dout3 ( dout3 )
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,.dout4 ( dout4 )
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,.dout5 ( dout5 )
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,.dout6 ( dout6 )
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,.dout7 ( dout7 )
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,.dout8 ( dout8 )
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,.dout9 ( dout9 )
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,.dout10 ( dout10 )
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,.dout11 ( dout11 )
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,.dout12 ( dout12 )
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,.dout13 ( dout13 )
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,.dout14 ( dout14 )
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,.dout15 ( dout15 )
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);
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endmodule
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