364 lines
12 KiB
Coq
364 lines
12 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : dacif.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.4 2024-03-12 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module dacif (
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input clk
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,input rstn
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//DAC mode select
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,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
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//2'b10:2xNRZ mode;2'b00:reserve;
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,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
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//3'b011:x8;3'b100:x16;
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,input din_vld
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,output dout_vld
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//mixer data input
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,input [15:0] din0
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,input [15:0] din1
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,input [15:0] din2
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,input [15:0] din3
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,input [15:0] din4
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,input [15:0] din5
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,input [15:0] din6
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,input [15:0] din7
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,input [15:0] din8
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,input [15:0] din9
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,input [15:0] din10
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,input [15:0] din11
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,input [15:0] din12
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,input [15:0] din13
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,input [15:0] din14
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,input [15:0] din15
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//data output
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,output [15:0] dout0
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,output [15:0] dout1
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,output [15:0] dout2
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,output [15:0] dout3
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,output [15:0] dout4
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,output [15:0] dout5
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,output [15:0] dout6
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,output [15:0] dout7
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,output [15:0] dout8
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,output [15:0] dout9
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,output [15:0] dout10
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,output [15:0] dout11
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,output [15:0] dout12
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,output [15:0] dout13
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,output [15:0] dout14
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,output [15:0] dout15
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);
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////////////////////////////////////////////////////
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// regs
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////////////////////////////////////////////////////
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reg [15:0] dout0_r ;
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reg [15:0] dout1_r ;
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reg [15:0] dout2_r ;
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reg [15:0] dout3_r ;
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reg [15:0] dout4_r ;
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reg [15:0] dout5_r ;
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reg [15:0] dout6_r ;
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reg [15:0] dout7_r ;
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reg [15:0] dout8_r ;
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reg [15:0] dout9_r ;
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reg [15:0] dout10_r;
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reg [15:0] dout11_r;
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reg [15:0] dout12_r;
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reg [15:0] dout13_r;
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reg [15:0] dout14_r;
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reg [15:0] dout15_r;
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reg [15:0] mux_p_0;
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reg [15:0] mux_p_1;
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reg [15:0] mux_p_2;
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reg [15:0] mux_p_3;
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reg [15:0] mux_p_4;
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reg [15:0] mux_p_5;
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reg [15:0] mux_p_6;
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reg [15:0] mux_p_7;
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reg [15:0] mux_p_8;
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reg [15:0] mux_p_9;
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reg [15:0] mux_p_a;
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reg [15:0] mux_p_b;
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reg [15:0] mux_p_c;
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reg [15:0] mux_p_d;
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reg [15:0] mux_p_e;
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reg [15:0] mux_p_f;
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reg [1:0] dacif_vld_dly;
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////////////////////////////////////////////////////
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// intp mode select
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////////////////////////////////////////////////////
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always@(posedge clk) begin
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case(intp_mode)
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3'b000 : begin
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mux_p_0 <= {~din15[15],din15[14:0]};
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mux_p_1 <= 16'h8000;
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mux_p_2 <= 16'h8000;
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mux_p_3 <= 16'h8000;
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mux_p_4 <= 16'h8000;
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mux_p_5 <= 16'h8000;
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mux_p_6 <= 16'h8000;
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mux_p_7 <= 16'h8000;
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mux_p_8 <= 16'h8000;
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mux_p_9 <= 16'h8000;
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mux_p_a <= 16'h8000;
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mux_p_b <= 16'h8000;
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mux_p_c <= 16'h8000;
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mux_p_d <= 16'h8000;
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mux_p_e <= 16'h8000;
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mux_p_f <= 16'h8000;
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end
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3'b001 : begin
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mux_p_0 <= {~din7[15],din7[14:0]};
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mux_p_1 <= {~din15[15],din15[14:0]};
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mux_p_2 <= 16'h8000 ;
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mux_p_3 <= 16'h8000 ;
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mux_p_4 <= 16'h8000 ;
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mux_p_5 <= 16'h8000 ;
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mux_p_6 <= 16'h8000 ;
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mux_p_7 <= 16'h8000 ;
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mux_p_8 <= 16'h8000 ;
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mux_p_9 <= 16'h8000 ;
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mux_p_a <= 16'h8000 ;
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mux_p_b <= 16'h8000 ;
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mux_p_c <= 16'h8000 ;
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mux_p_d <= 16'h8000 ;
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mux_p_e <= 16'h8000 ;
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mux_p_f <= 16'h8000 ;
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end
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3'b010 : begin
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mux_p_0 <= {~din3[15],din3[14:0]} ;
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mux_p_1 <= {~din7[15],din7[14:0]} ;
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mux_p_2 <= {~din11[15],din11[14:0]} ;
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mux_p_3 <= {~din15[15],din15[14:0]};
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mux_p_4 <= 16'h8000;
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mux_p_5 <= 16'h8000;
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mux_p_6 <= 16'h8000;
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mux_p_7 <= 16'h8000;
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mux_p_8 <= 16'h8000;
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mux_p_9 <= 16'h8000;
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mux_p_a <= 16'h8000;
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mux_p_b <= 16'h8000;
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mux_p_c <= 16'h8000;
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mux_p_d <= 16'h8000;
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mux_p_e <= 16'h8000;
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mux_p_f <= 16'h8000;
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end
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3'b011 : begin
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mux_p_0 <= {~din1[15],din1[14:0]} ;
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mux_p_1 <= {~din3[15],din3[14:0]} ;
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mux_p_2 <= {~din5[15],din5[14:0]} ;
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mux_p_3 <= {~din7[15],din7[14:0]} ;
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mux_p_4 <= {~din9[15],din9[14:0]} ;
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mux_p_5 <= {~din11[15],din11[14:0]};
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mux_p_6 <= {~din13[15],din13[14:0]};
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mux_p_7 <= {~din15[15],din15[14:0]};
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mux_p_8 <= 16'h8000 ;
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mux_p_9 <= 16'h8000 ;
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mux_p_a <= 16'h8000 ;
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mux_p_b <= 16'h8000 ;
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mux_p_c <= 16'h8000 ;
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mux_p_d <= 16'h8000 ;
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mux_p_e <= 16'h8000 ;
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mux_p_f <= 16'h8000 ;
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end
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3'b100 : begin
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mux_p_0 <= {~din0[15],din0[14:0]} ;
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mux_p_1 <= {~din1[15],din1[14:0]} ;
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mux_p_2 <= {~din2[15],din2[14:0]} ;
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mux_p_3 <= {~din3[15],din3[14:0]} ;
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mux_p_4 <= {~din4[15],din4[14:0]} ;
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mux_p_5 <= {~din5[15],din5[14:0]} ;
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mux_p_6 <= {~din6[15],din6[14:0]} ;
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mux_p_7 <= {~din7[15],din7[14:0]} ;
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mux_p_8 <= {~din8[15],din8[14:0]} ;
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mux_p_9 <= {~din9[15],din9[14:0]} ;
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mux_p_a <= {~din10[15],din10[14:0]};
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mux_p_b <= {~din11[15],din11[14:0]};
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mux_p_c <= {~din12[15],din12[14:0]};
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mux_p_d <= {~din13[15],din13[14:0]};
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mux_p_e <= {~din14[15],din14[14:0]};
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mux_p_f <= {~din15[15],din15[14:0]};
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end
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default : begin
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mux_p_0 <= 16'h8000;
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mux_p_1 <= 16'h8000;
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mux_p_2 <= 16'h8000;
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mux_p_3 <= 16'h8000;
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mux_p_4 <= 16'h8000;
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mux_p_5 <= 16'h8000;
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mux_p_6 <= 16'h8000;
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mux_p_7 <= 16'h8000;
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mux_p_8 <= 16'h8000;
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mux_p_9 <= 16'h8000;
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mux_p_a <= 16'h8000;
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mux_p_b <= 16'h8000;
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mux_p_c <= 16'h8000;
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mux_p_d <= 16'h8000;
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mux_p_e <= 16'h8000;
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mux_p_f <= 16'h8000;
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end
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endcase
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end
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////////////////////////////////////////////////////
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// mode select
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////////////////////////////////////////////////////
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always @(posedge clk or negedge rstn) begin
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if(rstn == 1'b0) begin
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dout0_r <= 16'h8000;
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dout1_r <= 16'h8000;
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dout2_r <= 16'h8000;
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dout3_r <= 16'h8000;
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dout4_r <= 16'h8000;
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dout5_r <= 16'h8000;
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dout6_r <= 16'h8000;
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dout7_r <= 16'h8000;
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dout8_r <= 16'h8000;
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dout9_r <= 16'h8000;
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dout10_r <= 16'h8000;
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dout11_r <= 16'h8000;
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dout12_r <= 16'h8000;
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dout13_r <= 16'h8000;
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dout14_r <= 16'h8000;
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dout15_r <= 16'h8000;
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end
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else begin
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case(dac_mode_sel)
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2'b00 : begin
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dout0_r <= mux_p_0;
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dout1_r <= mux_p_1;
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dout2_r <= mux_p_2;
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dout3_r <= mux_p_3;
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dout4_r <= mux_p_4;
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dout5_r <= mux_p_5;
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dout6_r <= mux_p_6;
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dout7_r <= mux_p_7;
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dout8_r <= mux_p_0;
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dout9_r <= mux_p_1;
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dout10_r <= mux_p_2;
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dout11_r <= mux_p_3;
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dout12_r <= mux_p_4;
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dout13_r <= mux_p_5;
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dout14_r <= mux_p_6;
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dout15_r <= mux_p_7;
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end
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2'b01 : begin
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dout0_r <= mux_p_0;
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dout1_r <= mux_p_1;
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dout2_r <= mux_p_2;
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dout3_r <= mux_p_3;
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dout4_r <= mux_p_4;
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dout5_r <= mux_p_5;
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dout6_r <= mux_p_6;
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dout7_r <= mux_p_7;
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dout8_r <= ~mux_p_0;
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dout9_r <= ~mux_p_1;
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dout10_r <= ~mux_p_2;
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dout11_r <= ~mux_p_3;
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dout12_r <= ~mux_p_4;
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dout13_r <= ~mux_p_5;
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dout14_r <= ~mux_p_6;
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dout15_r <= ~mux_p_7;
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end
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2'b10 : begin
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dout0_r <= mux_p_0;
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dout1_r <= mux_p_2;
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dout2_r <= mux_p_4;
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dout3_r <= mux_p_6;
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dout4_r <= mux_p_8;
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dout5_r <= mux_p_a;
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dout6_r <= mux_p_c;
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dout7_r <= mux_p_e;
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dout8_r <= mux_p_1;
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dout9_r <= mux_p_3;
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dout10_r <= mux_p_5;
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dout11_r <= mux_p_7;
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dout12_r <= mux_p_9;
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dout13_r <= mux_p_b;
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dout14_r <= mux_p_d;
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dout15_r <= mux_p_f;
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end
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2'b11 : begin
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dout0_r <= mux_p_0;
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dout1_r <= mux_p_1;
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dout2_r <= mux_p_2;
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dout3_r <= mux_p_3;
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dout4_r <= mux_p_4;
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dout5_r <= mux_p_5;
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dout6_r <= mux_p_6;
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dout7_r <= mux_p_7;
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dout8_r <= mux_p_8;
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dout9_r <= mux_p_9;
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dout10_r <= mux_p_a;
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dout11_r <= mux_p_b;
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dout12_r <= mux_p_c;
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dout13_r <= mux_p_d;
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dout14_r <= mux_p_e;
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dout15_r <= mux_p_f;
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end
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endcase
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end
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end
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|
|
|
||
|
|
assign dout0 = dout0_r ;
|
||
|
|
assign dout1 = dout1_r ;
|
||
|
|
assign dout2 = dout2_r ;
|
||
|
|
assign dout3 = dout3_r ;
|
||
|
|
assign dout4 = dout4_r ;
|
||
|
|
assign dout5 = dout5_r ;
|
||
|
|
assign dout6 = dout6_r ;
|
||
|
|
assign dout7 = dout7_r ;
|
||
|
|
assign dout8 = dout8_r ;
|
||
|
|
assign dout9 = dout9_r ;
|
||
|
|
assign dout10 = dout10_r ;
|
||
|
|
assign dout11 = dout11_r ;
|
||
|
|
assign dout12 = dout12_r ;
|
||
|
|
assign dout13 = dout13_r ;
|
||
|
|
assign dout14 = dout14_r ;
|
||
|
|
assign dout15 = dout15_r ;
|
||
|
|
|
||
|
|
//vld
|
||
|
|
always @(posedge clk or negedge rstn) begin
|
||
|
|
if(rstn == 1'b0) begin
|
||
|
|
dacif_vld_dly <= 2'b0;
|
||
|
|
end
|
||
|
|
else begin
|
||
|
|
dacif_vld_dly <= {dacif_vld_dly[0],din_vld};
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign dout_vld = dacif_vld_dly[1];
|
||
|
|
|
||
|
|
endmodule
|