32 lines
827 B
Systemverilog
32 lines
827 B
Systemverilog
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module sync_buf #(
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)(
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input logic clk,
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input logic rst_n,
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input logic ext_ena,
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input logic clr_ena,
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input logic clr_ena_sync,
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input logic sync_in,
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output logic sync_int,
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output logic sync_ext,
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output logic sync_clr
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);
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logic [2:0] sync_r;
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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sync_r[2:0] <= 3'b000;
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sync_int <= 1'b0;
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sync_ext <= 1'b0;
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end
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else begin
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sync_r[2:0] <= {sync_r[1:0],sync_in}; // delay two clock
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sync_int <= (sync_r[2:1] == 2'b01) & !clr_ena_sync; // detect pos edge
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sync_ext <= sync_r[2] & ext_ena; // sync input to clk
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end
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end
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assign sync_clr = ~(clr_ena & sync_in); // controlled buf out
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endmodule
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