SPI_Test/rtl/spi/spi_slave.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    spi_top.v
//  Department            :    
//  Author                :    pwy
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  1.2         2024-04-02       pwy           Integrate a digital module and two SPI modules with PLL
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//          
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//  Parameter
//
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module spi_slave (
  //system port
   input          clk               // System Main Clock
  ,input          rst_n             // Spi Reset active low
  //spi port                        
  ,input          sclk              // Spi Clock
  ,input          csn               // Spi Chip Select active low
  ,input          mosi              // Spi Mosi
  ,input  [4  :0] cfgid
  ,output         miso              // Spi Miso
  ,output         oen               // Spi Miso output enable
  //connect pll
  ,output [31 :0] pll_wrdata   
  ,output         pll_wren            
  ,output [7  :0] pll_rwaddr          
  ,output         pll_rden            
  ,input  [31 :0] pll_rddata
  //connect system
  ,output [31 :0] sys_wrdata   
  ,output         sys_wren            
  ,output [24 :0] sys_rwaddr          
  ,output         sys_rden            
  ,input  [31 :0] sys_rddata 
);

////////////////////////////////////////////////////////////////
// pll spi 
////////////////////////////////////////////////////////////////
wire pll_miso  ;     
wire pll_oen   ;
wire pll_sel   ;

spi_pll U_spi_pll            (
   .rst_n                    ( rst_n                    ) 
  ,.cfgid                    ( cfgid                    )
  ,.csn                      ( csn                      )
  ,.sclk                     ( sclk                     )
  ,.mosi                     ( mosi                     )
  ,.miso                     ( pll_miso                 )
  ,.oen                      ( pll_oen                  )
  ,.sel                      ( pll_sel                  )
  ,.wrdata                   ( pll_wrdata               )
  ,.wren                     ( pll_wren                 )
  ,.rwaddr                   ( pll_rwaddr               )
  ,.rden                     ( pll_rden                 )
  ,.rddata                   ( pll_rddata               )
);

////////////////////////////////////////////////////////////////
//sys pll
////////////////////////////////////////////////////////////////
wire sys_miso  ;     
wire sys_oen   ;
spi_sys U_spi_sys            (
   .clk                      ( clk                      )          
  ,.rst_n                    ( rst_n                    )
  ,.cfgid                    ( cfgid                    )
  ,.sclk                     ( sclk                     )
  ,.csn                      ( csn                      )
  ,.mosi                     ( mosi                     )
  ,.miso                     ( sys_miso                 )
  ,.oen                      ( sys_oen                  )
  ,.wrdata                   ( sys_wrdata               )
  ,.addr                     ( sys_rwaddr                 )
  ,.wren                     ( sys_wren                 )
  ,.rden                     ( sys_rden                 )
  ,.rddata                   ( sys_rddata               )
);

assign miso = pll_sel ?  pll_miso : sys_miso ; 
assign oen  = pll_sel ?  pll_oen  : sys_oen  ; 

endmodule