65 lines
2.5 KiB
Coq
65 lines
2.5 KiB
Coq
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`timescale 1ns/1ps
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//====================================================
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//Author : pwy
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//Date : 2024-04-04
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//Des : async set & sync release management unit
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//====================================================
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module rst_gen_unit(
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//ext hardware async reset -- low active
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input async_rstn_i
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//power-on reset -- low active
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,input por_rstn_i
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//sys soft reset -- low active
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,input sys_soft_resetn_i
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//ch0 soft reset -- low active
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,input ch0_soft_rstn_i
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//ch1 soft reset -- low active
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,input ch1_soft_rstn_i
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//ch2 soft reset -- low active
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,input ch2_soft_rstn_i
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//ch3 soft reset -- low active
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,input ch3_soft_rstn_i
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//clock
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,input clk
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//reset output -- low active
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,output ch0_rstn_o
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,output ch1_rstn_o
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,output ch2_rstn_o
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,output ch3_rstn_o
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//Phase-locked loop reset -- low active
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,output pll_rstn_o
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);
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//ch0 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch0_soft_rstn_i
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rst_sync ch0_rstn_sync (
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.clk_d ( clk )
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,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch0_soft_rstn_i )
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,.sync_rstn ( ch0_rstn_o )
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);
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//ch1 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch1_soft_rstn_i
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rst_sync ch1_rstn_sync (
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.clk_d ( clk )
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,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch1_soft_rstn_i )
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,.sync_rstn ( ch1_rstn_o )
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);
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//ch2 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch2_soft_rstn_i
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rst_sync ch2_rstn_sync (
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.clk_d ( clk )
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,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch2_soft_rstn_i )
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,.sync_rstn ( ch2_rstn_o )
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);
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//ch3 reset --> async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch3_soft_rstn_i
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rst_sync ch3_rstn_sync (
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.clk_d ( clk )
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,.async_rstn ( async_rstn_i & por_rstn_i & sys_soft_resetn_i & ch3_soft_rstn_i )
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,.sync_rstn ( ch3_rstn_o )
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);
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//Phase-locked loop reset -- low active
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assign pll_rstn_o = async_rstn_i & por_rstn_i;
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endmodule
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