90 lines
4.1 KiB
Coq
90 lines
4.1 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_exu_alu_ext.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY The Write-Back module to arbitrate the write-back request to regfile
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_wbck(
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//system port
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input clk
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,input rst_n
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//The enable signal from the master control state machine
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,input wbck_i_active
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//Write-back target register index from the decoding module
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,input [`QBMCU_RFIDX_WIDTH-1 :0] wbck_i_rdidx
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//Write enable for the write-back target register from the decoding module
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,input wbck_i_rdwen
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//////////////////////////////////////////////////////////////
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// The BJP Write-Back Interface
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,input [`QBMCU_XLEN-1 :0] bjp_i_wbck_wdat
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,input bjp_i_wbck_valid
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// The AGU Write-Back Interface
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,input [`QBMCU_XLEN-1 :0] agu_i_wbck_wdat
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,input agu_i_wbck_valid
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// The ALU Write-Back Interface
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,input [`QBMCU_XLEN-1 :0] alu_i_wbck_wdat
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,input alu_i_wbck_valid
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// The Ext Write-Back Interface
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,input [`QBMCU_XLEN-1 :0] ext_i_wbck_wdat
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,input ext_i_wbck_valid
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//////////////////////////////////////////////////////////////
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// The Final arbitrated Write-Back Interface to Regfile
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,output wbck_o_ena
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,output [`QBMCU_XLEN-1 :0] wbck_o_wdat
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,output [`QBMCU_RFIDX_WIDTH-1 :0] wbck_o_rdidx
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);
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//Write-back data multiplexer
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wire [`QBMCU_XLEN-1:0] wbck_i_wdat = {`QBMCU_XLEN{bjp_i_wbck_valid}} & bjp_i_wbck_wdat
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| {`QBMCU_XLEN{agu_i_wbck_valid}} & agu_i_wbck_wdat
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| {`QBMCU_XLEN{alu_i_wbck_valid}} & alu_i_wbck_wdat
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| {`QBMCU_XLEN{ext_i_wbck_valid}} & ext_i_wbck_wdat;
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//Assigning Write-back module output signal values
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wire wbck_o_ena_w = wbck_i_rdwen & wbck_i_active;
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sirv_gnrl_dffr #(1)wbck_o_ena_dffr (wbck_o_ena_w, wbck_o_ena, clk, rst_n);
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assign wbck_o_wdat = wbck_i_wdat[`QBMCU_XLEN-1:0];
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//assign wbck_o_rdidx = wbck_i_rdidx;
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sirv_gnrl_dfflr #(`QBMCU_RFIDX_WIDTH)wbck_o_rdidx_dfflr (wbck_i_active, wbck_i_rdidx, wbck_o_rdidx, clk, rst_n);
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endmodule
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`include "qbmcu_undefines.v"
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