271 lines
16 KiB
Coq
271 lines
16 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY Quantum Bit Measurement and Control Microprocessor
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu(
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//system port
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input clk
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,input rst_n
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//Sync Start
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,input qbmcu_i_start
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,output [2 :0] qbmcu_o_fsm_st
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//IFU port
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,input [`QBMCU_PC_SIZE-1 :0] ifu_i_pc_rtvec // Initial PC
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,output [`QBMCU_PC_SIZE-1 :0] ifu_o_req_pc // Fetch PC
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,output ifu_o_req // Fetch req
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,input [`QBMCU_INSTR_SIZE-1 :0] ifu_rsp_instr
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//Decoded port
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,output dec_o_ilegl
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//LDST port
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//Address, data, and enable signals connected to the memory space
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,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr
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,output [`QBMCU_XLEN-1 :0] agu_o_wrdata
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,output agu_o_wren // Write enable
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,output [`QBMCU_XLEN/8-1 :0] agu_o_wrmask
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,output agu_o_rden // Read enable
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,input [`QBMCU_XLEN-1 :0] agu_i_rddata
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//Misaligned memory address
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,output agu_o_addr_unalgn
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//Extend instructions port
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// The operands and info to peripheral
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,output ext_o_send
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,output ext_o_sendc
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,output [`QBMCU_XLEN-1 :0] ext_o_codeword
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,output ext_o_intr
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//qbmcu_fsm
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire ifupc_rst ;
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wire ifu_active ;
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wire wb_active ;
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wire dec_active ;
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wire exu_active ;
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wire ext_wait ;
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wire ext_o_exit ;
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wire qbmcu_i_timer_done ;
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qbmcu_fsm U_qbmcu_fsm (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.start ( qbmcu_i_start )
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,.exit ( ext_o_exit )
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,.ext_wait ( ext_wait )
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,.qbmcu_timer_done ( qbmcu_i_timer_done )
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,.agu_addr_unalgn ( agu_o_addr_unalgn )
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,.dec_ilegl ( dec_o_ilegl )
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,.ifupc_rst ( ifupc_rst )
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,.wb_active ( wb_active )
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,.ifu_active ( ifu_active )
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,.dec_active ( dec_active )
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,.exu_active ( exu_active )
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,.qbmcu_fsm_st ( qbmcu_o_fsm_st )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//qbmcu_ifu_ifetch
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir ;
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wire [`QBMCU_PC_SIZE-1 :0] ifu_pc ;
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wire update_pc_req ;
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wire [`QBMCU_PC_SIZE-1 :0] update_pc_value ;
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qbmcu_ifu U_qbmcu_ifu (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.ifu_active ( ifu_active )
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,.exu_active ( exu_active )
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,.pc_rtvec ( ifu_i_pc_rtvec )
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,.ifu_req_pc ( ifu_o_req_pc )
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,.ifu_req ( ifu_o_req )
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,.ifu_rsp_instr ( ifu_rsp_instr )
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,.ifu_o_ir ( ifu_ir )
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,.ifu_o_pc ( ifu_pc )
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,.ifupc_rst ( ifupc_rst )
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,.update_pc_req ( update_pc_req )
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,.update_pc_value ( update_pc_value )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//qbmcu_decode
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//wire dec_rs1en ;
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//wire dec_rs2en ;
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wire dec_rdwen ;
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wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs1idx ;
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wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rs2idx ;
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wire [`QBMCU_RFIDX_WIDTH-1 :0] dec_rdidx ;
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wire [`QBMCU_DECINFO_WIDTH-1:0] dec_info ;
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wire [`QBMCU_XLEN-1 :0] dec_imm ;
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wire [`QBMCU_PC_SIZE-1 :0] dec_pc ;
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qbmcu_decode qbmcu_decode (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.dec_i_active ( dec_active )
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,.dec_i_instr ( ifu_ir )
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,.dec_i_pc ( ifu_pc )
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//,.dec_o_rs1en ( dec_rs1en )
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//,.dec_o_rs2en ( dec_rs2en )
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,.dec_o_rdwen ( dec_rdwen )
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,.dec_o_rs1idx ( dec_rs1idx )
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,.dec_o_rs2idx ( dec_rs2idx )
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,.dec_o_rdidx ( dec_rdidx )
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,.dec_o_info ( dec_info )
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,.dec_o_imm ( dec_imm )
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,.dec_o_pc ( dec_pc )
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,.dec_o_ilegl ( dec_o_ilegl )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//qbmcu_exu
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire [`QBMCU_XLEN-1 :0] exu_rs1 ;
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wire [`QBMCU_XLEN-1 :0] exu_rs2 ;
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wire [`QBMCU_XLEN-1 :0] bjp_wbck_wdat ;
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wire bjp_wbck_valid ;
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wire [`QBMCU_XLEN-1 :0] agu_wbck_wdat ;
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wire agu_wbck_valid ;
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wire [`QBMCU_XLEN-1 :0] alu_wbck_wdat ;
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wire alu_wbck_valid ;
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wire [`QBMCU_XLEN-1 :0] ext_wbck_wdat ;
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wire ext_wbck_valid ;
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wire [`QBMCU_XLEN-1 :0] ext_wait_cnt ;
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//////////////////////////////////////////////////////////////
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//Address, data, and enable signals connected to the memory space
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wire ext_o_wait_valid ;
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qbmcu_exu U_qbmcu_exu (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.exu_i_rs1 ( exu_rs1 )
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,.exu_i_rs2 ( exu_rs2 )
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,.exu_i_imm ( dec_imm )
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,.exu_i_pc ( dec_pc )
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,.exu_i_info ( dec_info )
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,.exu_i_ilegl ( dec_o_ilegl )
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,.exu_i_active ( exu_active )
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,.bjp_o_wbck_wdat ( bjp_wbck_wdat )
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,.bjp_o_wbck_valid ( bjp_wbck_valid )
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,.bjp_update_pc_req ( update_pc_req )
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,.bjp_update_pc_value ( update_pc_value )
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,.ext_o_wait_valid ( ext_o_wait_valid )
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,.ext_o_wait ( ext_wait )
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,.ext_o_wait_cnt ( ext_wait_cnt )
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,.ext_o_send ( ext_o_send )
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,.ext_o_sendc ( ext_o_sendc )
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,.ext_o_codeword ( ext_o_codeword )
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,.ext_o_exit ( ext_o_exit )
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,.ext_o_intr ( ext_o_intr )
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,.ext_o_wbck_wdat ( ext_wbck_wdat )
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,.ext_o_wbck_valid ( ext_wbck_valid )
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,.agu_o_addr ( agu_o_addr )
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,.agu_o_wdata ( agu_o_wrdata )
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,.agu_o_wren ( agu_o_wren )
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,.agu_o_rden ( agu_o_rden )
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,.agu_o_wmask ( agu_o_wrmask )
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,.agu_i_rdata ( agu_i_rddata )
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,.agu_o_addr_unalgn ( agu_o_addr_unalgn )
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,.agu_o_wbck_wdat ( agu_wbck_wdat )
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,.agu_o_wbck_valid ( agu_wbck_valid )
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,.alu_o_wbck_wdat ( alu_wbck_wdat )
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,.alu_o_wbck_valid ( alu_wbck_valid )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//qbmcu_wbck
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire wbck_ena ;
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wire [`QBMCU_XLEN-1 :0] wbck_wdat ;
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wire [`QBMCU_RFIDX_WIDTH-1 :0] wbck_rdidx ;
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qbmcu_wbck U_qbmcu_wbck (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.wbck_i_active ( wb_active )
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,.wbck_i_rdidx ( dec_rdidx )
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,.wbck_i_rdwen ( dec_rdwen )
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,.bjp_i_wbck_wdat ( bjp_wbck_wdat )
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,.bjp_i_wbck_valid ( bjp_wbck_valid )
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,.agu_i_wbck_wdat ( agu_wbck_wdat )
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,.agu_i_wbck_valid ( agu_wbck_valid )
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,.alu_i_wbck_wdat ( alu_wbck_wdat )
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,.alu_i_wbck_valid ( alu_wbck_valid )
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,.ext_i_wbck_wdat ( ext_wbck_wdat )
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,.ext_i_wbck_valid ( ext_wbck_valid )
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,.wbck_o_ena ( wbck_ena )
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,.wbck_o_rdidx ( wbck_rdidx )
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,.wbck_o_wdat ( wbck_wdat )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//qbmcu_regfile
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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qbmcu_regfile U_qbmcu_regfile (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.read_src1_idx ( dec_rs1idx )
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,.read_src2_idx ( dec_rs2idx )
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,.read_src1_dat ( exu_rs1 )
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,.read_src2_dat ( exu_rs2 )
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,.wbck_dest_wen ( wbck_ena )
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,.wbck_dest_idx ( wbck_rdidx )
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,.wbck_dest_dat ( wbck_wdat )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//DW03_updn_ctr
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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defparam U_DW03_updn_ctr.width = 32;
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DW03_updn_ctr U_DW03_updn_ctr (
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.clk ( clk )// clock input
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,.reset ( rst_n )// asynchronous reset input (active low)
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,.data ( ext_wait_cnt-1'b1 )// data used for load operation
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,.up_dn ( 1'b0 )// up/down control input (0=down, 1-up)
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,.load ( !ext_wait )// load operation control input (active low)
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,.cen ( ext_o_wait_valid )// count enable control input (active high enable)
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,.count ( )// count value output
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,.tercnt ( qbmcu_i_timer_done ) // terminal count output flag (active high)
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);
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endmodule
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`include "qbmcu_undefines.v"
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