841 lines
37 KiB
Systemverilog
841 lines
37 KiB
Systemverilog
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : mcu_regfile.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY MCU dedicated register file
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//MCU parameter register 0
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`define MCUPARAR0 16'h00
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//MCU parameter register 1
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`define MCUPARAR1 16'h04
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//MCU parameter register 2
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`define MCUPARAR2 16'h08
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//MCU parameter register 3
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`define MCUPARAR3 16'h0C
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//MCU result register 0
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`define MCURESR0 16'h10
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//MCU result register 1
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`define MCURESR1 16'h14
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//MCU result register 2
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`define MCURESR2 16'h18
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//MCU result register 3
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`define MCURESR3 16'h1C
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//carrier frequency register 0
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`define CWFR0 16'h40
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//carrier frequency register 1
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`define CWFR1 16'h44
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//carrier frequency register 2
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`define CWFR2 16'h48
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//carrier frequency register 3
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`define CWFR3 16'h4C
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//carrier phase zeroing register
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`define CWPRR 16'h50
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//Gate-attached phase register 0
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`define GAPR0 16'h54
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//Gate-attached phase register 1
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`define GAPR1 16'h58
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//Gate-attached phase register 2
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`define GAPR2 16'h5C
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//Gate-attached phase register 3
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`define GAPR3 16'h60
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//Gate-attached phase register 4
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`define GAPR4 16'h64
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//Gate-attached phase register 5
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`define GAPR5 16'h68
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//Gate-attached phase register 6
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`define GAPR6 16'h6C
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//Gate-attached phase register 7
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`define GAPR7 16'h70
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//Line correction phase register
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`define LCPR 16'h74
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//Amplitude register 0
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`define AMPR0 16'h78
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//Amplitude register 1
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`define AMPR1 16'h7C
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//Amplitude register 2
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`define AMPR2 16'h80
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//Amplitude register 3
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`define AMPR3 16'h84
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//Bias Register 0
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`define BIASR0 16'h88
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//Bias Register 1
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`define BIASR1 16'h8C
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//Bias Register 2
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`define BIASR2 16'h90
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//Bias Register 3
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`define BIASR3 16'h94
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//Run-time register
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`define RTIMR 16'h98
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//Instruction count register
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`define ICNTR 16'h9C
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//Feedback state information register
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`define FSIR 16'hA0
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//Interpolator Selection Register
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`define INTPSELR 16'hA4
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module mcu_regfile (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [3 :0] wrmask
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,input [15 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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,input [1 :0] fb_st_info
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,input [31 :0] run_time
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,input [31 :0] instr_num
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//MCU and SPI interface for interaction
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,input [31 :0] mcu_param [3:0] // MCU parameter 0~3
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,output [31 :0] mcu_result [3:0] // MCU result 0~3
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//lookup table data
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,output [31 :0] mcu_cwfr [3:0] // Carrier frequency ctrl word 0~3
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,output [15 :0] mcu_gapr [7:0] // Carrier phase ctrl word 0~3
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,output [15 :0] mcu_ampr [3:0] // Carrier Amplitude 0~3
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,output [15 :0] mcu_baisr [3:0] // Carrier Bais 0~3
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//CFG Port
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,output [1 :0] mcu_intp_sel //2'b00:HBF;2'b01:Nearest-neighbor interpolator;
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,output mcu_nco_pha_clr
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,output [15 :0] mcu_rz_pha
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);
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localparam L = 1'b0,
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H = 1'b1;
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire mcuparar0en ; // MCUPARAR0 select
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wire mcuparar1en ; // MCUPARAR1 select
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wire mcuparar2en ; // MCUPARAR2 select
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wire mcuparar3en ; // MCUPARAR3 select
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wire mcuresr0en ; // MCURESR0 select
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wire mcuresr1en ; // MCURESR1 select
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wire mcuresr2en ; // MCURESR2 select
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wire mcuresr3en ; // MCURESR3 select
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wire cwfr0en ; // CWFR0 select
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wire cwfr1en ; // CWFR1 select
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wire cwfr2en ; // CWFR2 select
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wire cwfr3en ; // CWFR3 select
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wire cwprren ; // CWPRR select
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wire gapr0en ; // GAPR0 select
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wire gapr1en ; // GAPR1 select
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wire gapr2en ; // GAPR2 select
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wire gapr3en ; // GAPR3 select
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wire gapr4en ; // GAPR4 select
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wire gapr5en ; // GAPR5 select
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wire gapr6en ; // GAPR6 select
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wire gapr7en ; // GAPR7 select
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wire lcpren ; // LCPR select
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wire ampr0en ; // AMPR0 select
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wire ampr1en ; // AMPR1 select
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wire ampr2en ; // AMPR2 select
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wire ampr3en ; // AMPR3 select
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wire baisr0en ; // BIASR0 select
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wire baisr1en ; // BIASR1 select
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wire baisr2en ; // BIASR2 select
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wire baisr3en ; // BIASR3 select
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wire rtimren ; // RTIMR select
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wire icntren ; // ICNTR select
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wire fsiren ; // FSIR select
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wire intpselren ; // INTPSELR select
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire mcuresr0we ; // MCURESR0 write enable
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wire mcuresr1we ; // MCURESR1 write enable
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wire mcuresr2we ; // MCURESR2 write enable
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wire mcuresr3we ; // MCURESR3 write enable
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wire cwfr0we ; // CWFR0 write enable
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wire cwfr1we ; // CWFR1 write enable
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wire cwfr2we ; // CWFR2 write enable
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wire cwfr3we ; // CWFR3 write enable
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wire cwprrwe ; // CWPRR write enable
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wire gapr0we ; // GAPR0 write enable
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wire gapr1we ; // GAPR1 write enable
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wire gapr2we ; // GAPR2 write enable
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wire gapr3we ; // GAPR3 write enable
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wire gapr4we ; // GAPR4 write enable
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wire gapr5we ; // GAPR5 write enable
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wire gapr6we ; // GAPR6 write enable
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wire gapr7we ; // GAPR7 write enable
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wire lcprwe ; // LCPR write enable
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wire ampr0we ; // AMPR0 write enable
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wire ampr1we ; // AMPR1 write enable
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wire ampr2we ; // AMPR2 write enable
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wire ampr3we ; // AMPR3 write enable
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wire baisr0we ; // BIASR0 write enable
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wire baisr1we ; // BIASR1 write enable
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wire baisr2we ; // BIASR2 write enable
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wire baisr3we ; // BIASR3 write enable
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wire intpselrwe ; // INTPSELR select
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// ------------------------------------------------------
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// -- Misc wires
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// ------------------------------------------------------
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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wire [31 :0] mcuparar0 ; // MCUPARAR0 register
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wire [31 :0] mcuparar1 ; // MCUPARAR1 register
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wire [31 :0] mcuparar2 ; // MCUPARAR2 register
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wire [31 :0] mcuparar3 ; // MCUPARAR3 register
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wire [31 :0] mcuresr0 ; // MCURESR0 register
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wire [31 :0] mcuresr1 ; // MCURESR1 register
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wire [31 :0] mcuresr2 ; // MCURESR2 register
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wire [31 :0] mcuresr3 ; // MCURESR3 register
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wire [31 :0] cwfr0 ; // CWFR0 register
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wire [31 :0] cwfr1 ; // CWFR1 register
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wire [31 :0] cwfr2 ; // CWFR2 register
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wire [31 :0] cwfr3 ; // CWFR3 register
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wire [0 :0] cwprr ; // CWPRR register
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wire [15 :0] gapr0 ; // GAPR0 register////////////////////16bit but assign to 31:16?
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wire [15 :0] gapr1 ; // GAPR1 register
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wire [15 :0] gapr2 ; // GAPR2 register
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wire [15 :0] gapr3 ; // GAPR3 register
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wire [15 :0] gapr4 ; // GAPR4 register
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wire [15 :0] gapr5 ; // GAPR5 register
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wire [15 :0] gapr6 ; // GAPR6 register
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wire [15 :0] gapr7 ; // GAPR7 register
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wire [15 :0] lcpr ; // LCPR register
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wire [15 :0] ampr0 ; // AMPR0 register
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wire [15 :0] ampr1 ; // AMPR1 register
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wire [15 :0] ampr2 ; // AMPR2 register
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wire [15 :0] ampr3 ; // AMPR3 register
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wire [15 :0] baisr0 ; // BIASR0 register
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wire [15 :0] baisr1 ; // BIASR1 register
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wire [15 :0] baisr2 ; // BIASR2 register
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wire [15 :0] baisr3 ; // BIASR3 register
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wire [31 :0] rtimr ; // RTIMR register
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wire [31 :0] icntr ; // ICNTR register
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wire [1 :0] fsir ; // FSIR register
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wire [1 :0] intpselr ; // INTPSELR register
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reg [31: 0] rddata_reg ;
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// ------------------------------------------------------
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// -- Address decoder
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//
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// Decodes the register address offset input(reg_addr)
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// to produce enable (select) signals for each of the
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// SW-registers in the macrocell. The reg_addr input
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// is bits [15:0] of the paddr bus.
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// ------------------------------------------------------
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assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0;
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assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0;
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assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0;
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assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0;
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assign cwfr0en = (rwaddr[15:2] == `CWFR0 >> 2) ? 1'b1 : 1'b0;
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assign cwfr1en = (rwaddr[15:2] == `CWFR1 >> 2) ? 1'b1 : 1'b0;
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assign cwfr2en = (rwaddr[15:2] == `CWFR2 >> 2) ? 1'b1 : 1'b0;
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assign cwfr3en = (rwaddr[15:2] == `CWFR3 >> 2) ? 1'b1 : 1'b0;
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assign cwprren = (rwaddr[15:2] == `CWPRR >> 2) ? 1'b1 : 1'b0;
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assign gapr0en = (rwaddr[15:2] == `GAPR0 >> 2) ? 1'b1 : 1'b0;
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assign gapr1en = (rwaddr[15:2] == `GAPR1 >> 2) ? 1'b1 : 1'b0;
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assign gapr2en = (rwaddr[15:2] == `GAPR2 >> 2) ? 1'b1 : 1'b0;
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assign gapr3en = (rwaddr[15:2] == `GAPR3 >> 2) ? 1'b1 : 1'b0;
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assign gapr4en = (rwaddr[15:2] == `GAPR4 >> 2) ? 1'b1 : 1'b0;
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assign gapr5en = (rwaddr[15:2] == `GAPR5 >> 2) ? 1'b1 : 1'b0;
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assign gapr6en = (rwaddr[15:2] == `GAPR6 >> 2) ? 1'b1 : 1'b0;
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assign gapr7en = (rwaddr[15:2] == `GAPR7 >> 2) ? 1'b1 : 1'b0;
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assign lcpren = (rwaddr[15:2] == `LCPR >> 2) ? 1'b1 : 1'b0;
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assign ampr0en = (rwaddr[15:2] == `AMPR0 >> 2) ? 1'b1 : 1'b0;
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assign ampr1en = (rwaddr[15:2] == `AMPR1 >> 2) ? 1'b1 : 1'b0;
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assign ampr2en = (rwaddr[15:2] == `AMPR2 >> 2) ? 1'b1 : 1'b0;
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assign ampr3en = (rwaddr[15:2] == `AMPR3 >> 2) ? 1'b1 : 1'b0;
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assign baisr0en = (rwaddr[15:2] == `BIASR0 >> 2) ? 1'b1 : 1'b0;
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assign baisr1en = (rwaddr[15:2] == `BIASR1 >> 2) ? 1'b1 : 1'b0;
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assign baisr2en = (rwaddr[15:2] == `BIASR2 >> 2) ? 1'b1 : 1'b0;
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assign baisr3en = (rwaddr[15:2] == `BIASR3 >> 2) ? 1'b1 : 1'b0;
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assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0;
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assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0;
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assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0;
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assign intpselren = (rwaddr[15:2] == `INTPSELR >> 2) ? 1'b1 : 1'b0;
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// ------------------------------------------------------
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// -- Write enable signals
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//
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// Write enable signals for writable SW-registers.
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// The write enable for each register is the ANDed
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// result of the register enable and the input reg_wren
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// ------------------------------------------------------
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assign mcuresr0we = mcuresr0en & wren;
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assign mcuresr1we = mcuresr1en & wren;
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assign mcuresr2we = mcuresr2en & wren;
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assign mcuresr3we = mcuresr3en & wren;
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assign cwfr0we = cwfr0en & wren;
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assign cwfr1we = cwfr1en & wren;
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assign cwfr2we = cwfr2en & wren;
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assign cwfr3we = cwfr3en & wren;
|
||
|
|
assign cwprrwe = cwprren & wren;
|
||
|
|
assign gapr0we = gapr0en & wren;
|
||
|
|
assign gapr1we = gapr1en & wren;
|
||
|
|
assign gapr2we = gapr2en & wren;
|
||
|
|
assign gapr3we = gapr3en & wren;
|
||
|
|
assign gapr4we = gapr4en & wren;
|
||
|
|
assign gapr5we = gapr5en & wren;
|
||
|
|
assign gapr6we = gapr6en & wren;
|
||
|
|
assign gapr7we = gapr7en & wren;
|
||
|
|
assign lcprwe = lcpren & wren;
|
||
|
|
assign ampr0we = ampr0en & wren;
|
||
|
|
assign ampr1we = ampr1en & wren;
|
||
|
|
assign ampr2we = ampr2en & wren;
|
||
|
|
assign ampr3we = ampr3en & wren;
|
||
|
|
assign baisr0we = baisr0en & wren;
|
||
|
|
assign baisr1we = baisr1en & wren;
|
||
|
|
assign baisr2we = baisr2en & wren;
|
||
|
|
assign baisr3we = baisr3en & wren;
|
||
|
|
assign intpselrwe = intpselren & wren;
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr0 register
|
||
|
|
//
|
||
|
|
// Write mcuresr0 for 'MCURESR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuresr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] mcuresr0_w;
|
||
|
|
assign mcuresr0_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr0[31:24];
|
||
|
|
assign mcuresr0_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr0[23:16];
|
||
|
|
assign mcuresr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr0[15 :8];
|
||
|
|
assign mcuresr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr0[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) mcuresr0_dfflr (mcuresr0we, mcuresr0_w[31:0], mcuresr0, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr1 register
|
||
|
|
//
|
||
|
|
// Write mcuresr1 for 'MCURESR1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuresr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] mcuresr1_w;
|
||
|
|
assign mcuresr1_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr1[31:24];
|
||
|
|
assign mcuresr1_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr1[23:16];
|
||
|
|
assign mcuresr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr1[15 :8];
|
||
|
|
assign mcuresr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr1[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) mcuresr1_dfflr (mcuresr1we, mcuresr1_w[31:0], mcuresr1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr2 register
|
||
|
|
//
|
||
|
|
// Write mcuresr2 for 'MCURESR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuresr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] mcuresr2_w;
|
||
|
|
assign mcuresr2_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr2[31:24];
|
||
|
|
assign mcuresr2_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr2[23:16];
|
||
|
|
assign mcuresr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr2[15 :8];
|
||
|
|
assign mcuresr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr2[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) mcuresr2_dfflr (mcuresr2we, mcuresr2_w[31:0], mcuresr2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr3 register
|
||
|
|
//
|
||
|
|
// Write mcuresr3 for 'MCURESR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuresr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] mcuresr3_w;
|
||
|
|
assign mcuresr3_w[31:24] = wrmask[3] ? wrdata[31:24] : mcuresr3[31:24];
|
||
|
|
assign mcuresr3_w[23:16] = wrmask[2] ? wrdata[23:16] : mcuresr3[23:16];
|
||
|
|
assign mcuresr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : mcuresr3[15 :8];
|
||
|
|
assign mcuresr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : mcuresr3[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) mcuresr3_dfflr (mcuresr3we, mcuresr3_w[31:0], mcuresr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- cwfr0 register
|
||
|
|
//
|
||
|
|
// Write cwfr0 for 'CWFR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> cwfr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] cwfr0_w;
|
||
|
|
assign cwfr0_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr0[31:24];
|
||
|
|
assign cwfr0_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr0[23:16];
|
||
|
|
assign cwfr0_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr0[15 :8];
|
||
|
|
assign cwfr0_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr0[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) cwfr0_dfflr (cwfr0we, cwfr0_w[31:0], cwfr0, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- cwfr1 register
|
||
|
|
//
|
||
|
|
// Write cwfr1 for 'CWFR1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> cwfr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] cwfr1_w;
|
||
|
|
assign cwfr1_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr1[31:24];
|
||
|
|
assign cwfr1_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr1[23:16];
|
||
|
|
assign cwfr1_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr1[15 :8];
|
||
|
|
assign cwfr1_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr1[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) cwfr1_dfflr (cwfr1we, cwfr1_w[31:0], cwfr1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- cwfr2 register
|
||
|
|
//
|
||
|
|
// Write cwfr2 for 'CWFR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> cwfr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] cwfr2_w;
|
||
|
|
assign cwfr2_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr2[31:24];
|
||
|
|
assign cwfr2_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr2[23:16];
|
||
|
|
assign cwfr2_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr2[15 :8];
|
||
|
|
assign cwfr2_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr2[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) cwfr2_dfflr (cwfr2we, cwfr2_w[31:0], cwfr2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- cwfr3 register
|
||
|
|
//
|
||
|
|
// Write cwfr3 for 'CWFR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> cwfr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] cwfr3_w;
|
||
|
|
assign cwfr3_w[31:24] = wrmask[3] ? wrdata[31:24] : cwfr3[31:24];
|
||
|
|
assign cwfr3_w[23:16] = wrmask[2] ? wrdata[23:16] : cwfr3[23:16];
|
||
|
|
assign cwfr3_w[15 :8] = wrmask[1] ? wrdata[15 :8] : cwfr3[15 :8];
|
||
|
|
assign cwfr3_w[7 :0] = wrmask[0] ? wrdata[7 :0] : cwfr3[7 :0];
|
||
|
|
sirv_gnrl_dfflr #(32) cwfr3_dfflr (cwfr3we, cwfr3_w[31:0], cwfr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- cwprr register(self-clearing)
|
||
|
|
//
|
||
|
|
// Write cwprr for 'CWPRR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> cwprr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire cwprr_w = wrmask[0] & cwprrwe & wrdata[0];
|
||
|
|
|
||
|
|
sirv_gnrl_dffr #(1) cwprr_dffr (cwprr_w, cwprr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr0 register
|
||
|
|
//
|
||
|
|
// Write gapr0 for 'GAPR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr0_w;
|
||
|
|
assign gapr0_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr0[15: 8];/////////////////////////////////////////////////////////////31:26->15:8
|
||
|
|
assign gapr0_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr0[ 7: 0];/////////////////////////////////////////////////////////////23:16->7:0
|
||
|
|
sirv_gnrl_dfflr #(16) gapr0_dfflr (gapr0we, gapr0_w[31:16], gapr0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr1 register
|
||
|
|
//
|
||
|
|
// Write gapr1 for 'GAPR1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr1_w;
|
||
|
|
assign gapr1_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr1[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr1_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr1_dfflr (gapr1we, gapr1_w[31:16], gapr1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr2 register
|
||
|
|
//
|
||
|
|
// Write gapr2 for 'GAPR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr2_w;
|
||
|
|
assign gapr2_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr2[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr2_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr2_dfflr (gapr2we, gapr2_w[31:16], gapr2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr3 register
|
||
|
|
//
|
||
|
|
// Write gapr3 for 'GAPR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr3_w;
|
||
|
|
assign gapr3_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr3[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr3_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr3_dfflr (gapr3we, gapr3_w[31:16], gapr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr4 register
|
||
|
|
//
|
||
|
|
// Write gapr4 for 'GAPR4' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr4
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr4_w;
|
||
|
|
assign gapr4_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr4[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr4_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr4[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr4_dfflr (gapr4we, gapr4_w[31:16], gapr4, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr5 register
|
||
|
|
//
|
||
|
|
// Write gapr5 for 'GAPR5' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr5
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr5_w;
|
||
|
|
assign gapr5_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr5[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr5_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr5[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr5_dfflr (gapr5we, gapr5_w[31:16], gapr5, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr6 register
|
||
|
|
//
|
||
|
|
// Write gapr6 for 'GAPR6' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr6
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr6_w;
|
||
|
|
assign gapr6_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr6[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr6_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr6[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr6_dfflr (gapr6we, gapr6_w[31:16], gapr6, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- gapr7 register
|
||
|
|
//
|
||
|
|
// Write gapr7 for 'GAPR7' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> gapr7
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] gapr7_w;
|
||
|
|
assign gapr7_w[31:24] = wrmask[3] ? wrdata[31:24] : gapr7[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign gapr7_w[23:16] = wrmask[2] ? wrdata[23:16] : gapr7[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) gapr7_dfflr (gapr7we, gapr7_w[31:16], gapr7, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- lcpr register
|
||
|
|
//
|
||
|
|
// Write lcpr for 'LCPR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> lcpr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] lcpr_w;
|
||
|
|
assign lcpr_w[31:24] = wrmask[3] ? wrdata[31:24] : lcpr[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign lcpr_w[23:16] = wrmask[2] ? wrdata[23:16] : lcpr[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) lcpr_dfflr (lcprwe, lcpr_w[31:16], lcpr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- ampr0 register
|
||
|
|
//
|
||
|
|
// Write ampr0 for 'AMPR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> ampr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] ampr0_w;
|
||
|
|
assign ampr0_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr0[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign ampr0_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr0[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) ampr0_dfflr (ampr0we, ampr0_w[31:16], ampr0, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- ampr1 register
|
||
|
|
//
|
||
|
|
// Write ampr1 for 'AMPR10' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> ampr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] ampr1_w;
|
||
|
|
assign ampr1_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr1[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign ampr1_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) ampr1_dfflr (ampr1we, ampr1_w[31:16], ampr1, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- ampr2 register
|
||
|
|
//
|
||
|
|
// Write ampr2 for 'AMPR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> ampr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] ampr2_w;
|
||
|
|
assign ampr2_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr2[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign ampr2_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) ampr2_dfflr (ampr2we, ampr2_w[31:16], ampr2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- ampr3 register
|
||
|
|
//
|
||
|
|
// Write ampr3 for 'AMPR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> ampr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] ampr3_w;
|
||
|
|
assign ampr3_w[31:24] = wrmask[3] ? wrdata[31:24] : ampr3[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign ampr3_w[23:16] = wrmask[2] ? wrdata[23:16] : ampr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) ampr3_dfflr (ampr3we, ampr3_w[31:16], ampr3, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- baisr0 register
|
||
|
|
//
|
||
|
|
// Write baisr0 for 'BIASR0' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> baisr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] baisr0_w;
|
||
|
|
assign baisr0_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr0[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign baisr0_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr0[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) baisr0_dfflr (baisr0we, baisr0_w[31:16], baisr0, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- baisr1 register
|
||
|
|
//
|
||
|
|
// Write baisr1 for 'BIASR1' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> baisr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] baisr1_w;
|
||
|
|
assign baisr1_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr1[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign baisr1_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr1[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) baisr1_dfflr (baisr1we, baisr1_w[31:16], baisr1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- baisr2 register
|
||
|
|
//
|
||
|
|
// Write baisr2 for 'BIASR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> baisr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] baisr2_w;
|
||
|
|
assign baisr2_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr2[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign baisr2_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr2[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) baisr2_dfflr (baisr2we, baisr2_w[31:16], baisr2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- baisr3 register
|
||
|
|
//
|
||
|
|
// Write baisr3 for 'BIASR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> baisr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [31:0] baisr3_w;
|
||
|
|
assign baisr3_w[31:24] = wrmask[3] ? wrdata[31:24] : baisr3[15: 8];/////////////////////////////////////////////////////////////
|
||
|
|
assign baisr3_w[23:16] = wrmask[2] ? wrdata[23:16] : baisr3[ 7: 0];/////////////////////////////////////////////////////////////
|
||
|
|
sirv_gnrl_dfflr #(16) baisr3_dfflr (baisr3we, baisr3_w[31:16], baisr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- intpselr register
|
||
|
|
//
|
||
|
|
// Write intpselr for 'INTPSELR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1:0] --> intpselr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
wire [1:0] intpselr_w;
|
||
|
|
assign intpselr_w[1:0] = wrmask[0] ? wrdata[1:0] : intpselr[1:0];
|
||
|
|
sirv_gnrl_dfflr #(2) intpselr_dfflr (intpselrwe, intpselr_w[1:0], intpselr, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_param[0], mcuparar0, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_param[1], mcuparar1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_param[2], mcuparar2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_param[3], mcuparar3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- rtimr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- icntr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- fsir
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(2) fsir_dffr (fb_st_info[1:0], fsir, clk, rst_n);////////////////////////////////////////////[1:0]
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Read data mux
|
||
|
|
//
|
||
|
|
// -- The data from the selected register is
|
||
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
||
|
|
// ------------------------------------------------------
|
||
|
|
always @(*) begin : RDDATA_PROC
|
||
|
|
rddata_reg = {32{1'b0}};
|
||
|
|
if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ;
|
||
|
|
if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ;
|
||
|
|
if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ;
|
||
|
|
if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ;
|
||
|
|
if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ;
|
||
|
|
if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ;
|
||
|
|
if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ;
|
||
|
|
if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ;
|
||
|
|
if(cwfr0en == H ) rddata_reg[31:0] = cwfr0 ;
|
||
|
|
if(cwfr1en == H ) rddata_reg[31:0] = cwfr1 ;
|
||
|
|
if(cwfr2en == H ) rddata_reg[31:0] = cwfr2 ;
|
||
|
|
if(cwfr3en == H ) rddata_reg[31:0] = cwfr3 ;
|
||
|
|
if(cwprren == H ) rddata_reg[0 :0] = cwprr ;
|
||
|
|
if(gapr0en == H ) rddata_reg[15:0] = gapr0 ;
|
||
|
|
if(gapr1en == H ) rddata_reg[15:0] = gapr1 ;
|
||
|
|
if(gapr2en == H ) rddata_reg[15:0] = gapr2 ;
|
||
|
|
if(gapr3en == H ) rddata_reg[15:0] = gapr3 ;
|
||
|
|
if(gapr4en == H ) rddata_reg[15:0] = gapr4 ;
|
||
|
|
if(gapr5en == H ) rddata_reg[15:0] = gapr5 ;
|
||
|
|
if(gapr6en == H ) rddata_reg[15:0] = gapr6 ;
|
||
|
|
if(gapr7en == H ) rddata_reg[15:0] = gapr7 ;
|
||
|
|
if(lcpren == H ) rddata_reg[15:0] = lcpr ;
|
||
|
|
if(ampr0en == H ) rddata_reg[15:0] = ampr0 ;
|
||
|
|
if(ampr1en == H ) rddata_reg[15:0] = ampr1 ;
|
||
|
|
if(ampr2en == H ) rddata_reg[15:0] = ampr2 ;
|
||
|
|
if(ampr3en == H ) rddata_reg[15:0] = ampr3 ;
|
||
|
|
if(baisr0en == H ) rddata_reg[15:0] = baisr0 ;
|
||
|
|
if(baisr1en == H ) rddata_reg[15:0] = baisr1 ;
|
||
|
|
if(baisr2en == H ) rddata_reg[15:0] = baisr2 ;
|
||
|
|
if(baisr3en == H ) rddata_reg[15:0] = baisr3 ;
|
||
|
|
if(rtimren == H ) rddata_reg[31:0] = rtimr ;
|
||
|
|
if(icntren == H ) rddata_reg[31:0] = icntr ;
|
||
|
|
if(fsiren == H ) rddata_reg[1 :0] = fsir ;
|
||
|
|
if(intpselren == H ) rddata_reg[1 :0] = intpselr ;////////////////////////////////////////////////////////////
|
||
|
|
end
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Output signals assignment
|
||
|
|
// ------------------------------------------------------
|
||
|
|
//mcu result
|
||
|
|
assign mcu_result[0] = mcuresr0 ;
|
||
|
|
assign mcu_result[1] = mcuresr1 ;
|
||
|
|
assign mcu_result[2] = mcuresr2 ;
|
||
|
|
assign mcu_result[3] = mcuresr3 ;
|
||
|
|
|
||
|
|
//nco_fwc lookup table output
|
||
|
|
assign mcu_cwfr[0] = cwfr0;
|
||
|
|
assign mcu_cwfr[1] = cwfr1;
|
||
|
|
assign mcu_cwfr[2] = cwfr2;
|
||
|
|
assign mcu_cwfr[3] = cwfr3;
|
||
|
|
|
||
|
|
//nco_pha lookup table output
|
||
|
|
assign mcu_gapr[0] = gapr0; ////////////////////////////////////////////////16bit assign to 32bit(?)
|
||
|
|
assign mcu_gapr[1] = gapr1;
|
||
|
|
assign mcu_gapr[2] = gapr2;
|
||
|
|
assign mcu_gapr[3] = gapr3;
|
||
|
|
assign mcu_gapr[4] = gapr4;
|
||
|
|
assign mcu_gapr[5] = gapr5;
|
||
|
|
assign mcu_gapr[6] = gapr6;
|
||
|
|
assign mcu_gapr[7] = gapr7;
|
||
|
|
|
||
|
|
//amp lookup table output
|
||
|
|
assign mcu_ampr[0] = ampr0;
|
||
|
|
assign mcu_ampr[1] = ampr1;
|
||
|
|
assign mcu_ampr[2] = ampr2;
|
||
|
|
assign mcu_ampr[3] = ampr3;
|
||
|
|
|
||
|
|
//bais lookup table output
|
||
|
|
assign mcu_baisr[0] = baisr0;
|
||
|
|
assign mcu_baisr[1] = baisr1;
|
||
|
|
assign mcu_baisr[2] = baisr2;
|
||
|
|
assign mcu_baisr[3] = baisr3;
|
||
|
|
|
||
|
|
//CFG Port
|
||
|
|
assign mcu_nco_pha_clr = cwprr;
|
||
|
|
assign mcu_rz_pha = lcpr;
|
||
|
|
assign mcu_intp_sel = intpselr;
|
||
|
|
//rddata
|
||
|
|
//assign rddata = rddata_reg ;
|
||
|
|
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);////////////////////////
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
`undef MCUPARAR0
|
||
|
|
`undef MCUPARAR1
|
||
|
|
`undef MCUPARAR2
|
||
|
|
`undef MCUPARAR3
|
||
|
|
`undef MCURESR0
|
||
|
|
`undef MCURESR1
|
||
|
|
`undef MCURESR2
|
||
|
|
`undef MCURESR3
|
||
|
|
`undef CWFR0
|
||
|
|
`undef CWFR1
|
||
|
|
`undef CWFR2
|
||
|
|
`undef CWFR3
|
||
|
|
`undef CWPRR
|
||
|
|
`undef GAPR0
|
||
|
|
`undef GAPR1
|
||
|
|
`undef GAPR2
|
||
|
|
`undef GAPR3
|
||
|
|
`undef GAPR4
|
||
|
|
`undef GAPR5
|
||
|
|
`undef GAPR6
|
||
|
|
`undef GAPR7
|
||
|
|
`undef LCPR
|
||
|
|
`undef AMPR0
|
||
|
|
`undef AMPR1
|
||
|
|
`undef AMPR2
|
||
|
|
`undef AMPR3
|
||
|
|
`undef BIASR0
|
||
|
|
`undef BIASR1
|
||
|
|
`undef BIASR2
|
||
|
|
`undef BIASR3
|
||
|
|
`undef RTIMR
|
||
|
|
`undef ICNTR
|
||
|
|
`undef FSIR
|