SPI_Test/rtl/perips/qbmcu_busdecoder.v

//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    qbmcu_busdecoder.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  1.0         2022-08-25      PWY
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

`include "../qubitmcu/qbmcu_defines.v"

module qbmcu_busdecoder #(
   parameter S0_BASEADDR = 32'h0010_0000
  ,parameter S1_BASEADDR = 32'h0020_0000
)(
   //rw op port
   input                         wren            // write enable
  ,input  [`QBMCU_XLEN/8-1   :0] wrmask          // write mask
  ,input  [`QBMCU_XLEN-1     :0] wrdata          // write data
  ,input  [`QBMCU_ADDR_SIZE-1:0] rwaddr          // read & write addr
  ,input                         rden            // read enable
  ,output [`QBMCU_XLEN-1     :0] rddata          // read data
  //data sram read and write signals    
  ,output                        s0_wren         // s0 write enable
  ,output [`QBMCU_XLEN/8-1   :0] s0_wrmask       // write mask
  ,output [`QBMCU_ADDR_SIZE-1:0] s0_rwaddr       // s0 read & write addr
  ,output [`QBMCU_XLEN-1     :0] s0_wrdata       // s0 write data
  ,output                        s0_rden         // s0 read enable
  ,input  [`QBMCU_XLEN-1     :0] s0_rddata       // s0 read data
  //mcu perips reg read and write signals
  ,output                        s1_wren         // s1 write enable
  ,output [`QBMCU_XLEN/8-1   :0] s1_wrmask       // write mask
  ,output [`QBMCU_ADDR_SIZE-1:0] s1_rwaddr       // s1 read & write addr
  ,output [`QBMCU_XLEN-1     :0] s1_wrdata       // s1 write data
  ,output                        s1_rden         // s1 read enable
  ,input  [`QBMCU_XLEN-1     :0] s1_rddata       // s1 read data
);

wire       s0_sel;
wire       s1_sel;

//s0_sel
assign s0_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S0_BASEADDR >> 16);
//s1_sel
assign s1_sel = (rwaddr[`QBMCU_ADDR_SIZE-1:16] == S1_BASEADDR >> 16);


//s0_wren
assign s0_wren = s0_sel & wren;
//s1_wren
assign s1_wren = s1_sel & wren;

//s0_wrmask
assign s0_wrmask = {`QBMCU_XLEN/8{s0_sel}} & wrmask;
//s1_wrmask
assign s1_wrmask = {`QBMCU_XLEN/8{s1_sel}} & wrmask;

//s0_rden
assign s0_rden = s0_sel & rden;
//s1_rden
assign s1_rden = s1_sel & rden;


//s0_rwaddr
assign s0_rwaddr = {`QBMCU_ADDR_SIZE{s0_sel}} & rwaddr;
//s1_rwaddr
assign s1_rwaddr = {`QBMCU_ADDR_SIZE{s1_sel}} & rwaddr;

//s0_wrdata
assign s0_wrdata = {`QBMCU_XLEN{s0_sel}} & wrdata;
//s1_wrdata                          
assign s1_wrdata = {`QBMCU_XLEN{s1_sel}} & wrdata;

// ------------------------------------------------------
// -- Read data mux
//
// -- The data from the selected register is
// -- placed on a zero-padded 32-bit read data bus.
// ------------------------------------------------------

wire [`QBMCU_XLEN-1:0] rddata_w = {`QBMCU_XLEN{s0_sel}} & s0_rddata 
                                | {`QBMCU_XLEN{s1_sel}} & s1_rddata;

//rddata
assign rddata = rddata_w;

endmodule

`include "../qubitmcu/qbmcu_undefines.v"