157 lines
14 KiB
Coq
157 lines
14 KiB
Coq
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/07/03 13:29:31
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// Design Name:
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// Module Name: xil_tdpram
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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//`define XINLINX_FPGA
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module xil_tdpram #(
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parameter DATAWIDTH = 32
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,parameter ADDRWIDTH = 12
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)(
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input PortClk
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,input [ADDRWIDTH-1 :0] PortAAddr
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,input [DATAWIDTH-1 :0] PortADataIn
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,input PortAWriteEnable //active low
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,input PortAChipEnable //active low
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,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
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,output [DATAWIDTH-1 :0] PortADataOut
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,input [ADDRWIDTH-1 :0] PortBAddr
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,input [DATAWIDTH-1 :0] PortBDataIn
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,input PortBWriteEnable //active low
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,input PortBChipEnable //active low
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,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
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,output [DATAWIDTH-1 :0] PortBDataOut
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);
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////////////////////////////////////////////////////////////////////////////////
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//Function
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////////////////////////////////////////////////////////////////////////////////
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function integer clog2(input integer bit_depth);
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begin
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for(clog2=0;bit_depth>0;clog2=clog2+1)
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bit_depth =bit_depth>>1;
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end
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endfunction
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localparam LSB = clog2(DATAWIDTH/8 -1);
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localparam MAW = ADDRWIDTH - LSB;
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localparam MB =(DATAWIDTH)*(32'h0000_0001<<MAW);
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////////////////////////////////////////////////////////////////////////////////
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//XPM
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////////////////////////////////////////////////////////////////////////////////
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wire [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable_w = {(DATAWIDTH/8){PortAWriteEnable | PortAChipEnable}} | PortAByteWriteEnable;
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wire [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable_w = {(DATAWIDTH/8){PortBWriteEnable | PortBChipEnable}} | PortBByteWriteEnable;
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xpm_memory_tdpram #(
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.CLOCKING_MODE ( "common_clock" ) // String
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,.ECC_MODE ( "no_ecc" ) // String
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,.MEMORY_INIT_FILE ( "none" ) // String
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,.MEMORY_INIT_PARAM ( "0" ) // String
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,.MEMORY_OPTIMIZATION ( "true" ) // String
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,.MEMORY_PRIMITIVE ( "auto" ) // String
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,.AUTO_SLEEP_TIME ( 0 ) // DECIMAL
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,.CASCADE_HEIGHT ( 0 ) // DECIMAL
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,.SIM_ASSERT_CHK ( 0 ) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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,.USE_EMBEDDED_CONSTRAINT ( 0 ) // DECIMAL
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,.USE_MEM_INIT ( 1 ) // DECIMAL
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,.WAKEUP_TIME ( "disable_sleep" ) // String
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,.MESSAGE_CONTROL ( 0 ) // DECIMAL
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,.MEMORY_SIZE ( MB ) // DECIMAL
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,.ADDR_WIDTH_A ( MAW ) // DECIMAL
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,.BYTE_WRITE_WIDTH_A ( 8 ) // DECIMAL
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,.WRITE_DATA_WIDTH_A ( DATAWIDTH ) // DECIMAL
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,.READ_DATA_WIDTH_A ( DATAWIDTH ) // DECIMAL
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,.READ_LATENCY_A ( 1 ) // DECIMAL
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,.READ_RESET_VALUE_A ( "0" ) // String
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,.RST_MODE_A ( "SYNC" ) // String
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,.WRITE_MODE_A ( "no_change" ) // String
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,.ADDR_WIDTH_B ( MAW ) // DECIMAL
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,.BYTE_WRITE_WIDTH_B ( 8 ) // DECIMAL
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,.WRITE_DATA_WIDTH_B ( DATAWIDTH ) // DECIMAL
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,.READ_DATA_WIDTH_B ( DATAWIDTH ) // DECIMAL
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,.READ_LATENCY_B ( 1 ) // DECIMAL
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,.READ_RESET_VALUE_B ( "0" ) // String
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,.RST_MODE_B ( "SYNC" ) // String
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,.WRITE_MODE_B ( "no_change" ) // String
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) xpm_memory_tdpram_inst (
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.rsta ( 0 ) // 1-bit input: Reset signal for the final port A output register stage.
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// Synchronously resets output port douta to the value specified by
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// parameter READ_RESET_VALUE_A.
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,.clka ( PortClk ) // 1-bit input: Clock signal for port A. Also clocks port B when
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// parameter CLOCKING_MODE is "common_clock".
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,.regcea ( 0 ) // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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,.ena ( 1'b1 ) // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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,.wea ( ~PortAByteWriteEnable_w ) // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
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// for port A input data port dina. 1 bit wide when word-wide writes are
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// used. In byte-wide write configurations, each bit controls the
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// writing one byte of dina to address addra. For example, to
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// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
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// is 32, wea would be 4'b0010.
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,.addra ( PortAAddr[ADDRWIDTH-1 : LSB] ) // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
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,.dina ( PortADataIn ) // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
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,.douta ( PortADataOut ) // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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,.dbiterra ( ) // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port A.
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,.sbiterra ( ) // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port A.
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,.injectdbiterra ( 1'b0 ) // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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,.injectsbiterra ( 1'b0 ) // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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,.rstb ( 0 ) // 1-bit input: Reset signal for the final port B output register stage.
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// Synchronously resets output port douta to the value specified by
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// parameter READ_RESET_VALUE_B.
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,.clkb ( PortClk ) // 1-bit input: Clock signal for port B. Also clocks port A when
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// parameter CLOCKING_MODE is "common_clock".
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,.regceb ( 0 ) // 1-bit input: Clock Enable for the last register stage on the output
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// data path.
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,.enb ( 1'b1 ) // 1-bit input: Memory enable signal for port B. Must be high on clock
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// cycles when read or write operations are initiated. Pipelined
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// internally.
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,.web ( ~PortBByteWriteEnable_w ) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
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// for port B input data port dina. 1 bit wide when word-wide writes are
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// used. In byte-wide write configurations, each bit controls the
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// writing one byte of dinb to address addrb. For example, to
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// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_B
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// is 32, wea would be 4'b0010.
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,.addrb ( PortBAddr[ADDRWIDTH-1 : LSB] ) // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
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,.dinb ( PortBDataIn ) // WRITE_DATA_WIDTH_A-bit input: Data input for port B write operations.
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,.doutb ( PortBDataOut ) // READ_DATA_WIDTH_A-bit output: Data output for port B read operations.
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,.dbiterrb ( ) // 1-bit output: Status signal to indicate double bit error occurrence
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// on the data output of port B.
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,.sbiterrb ( ) // 1-bit output: Status signal to indicate single bit error occurrence
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// on the data output of port B.
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,.injectdbiterrb ( 1'b0 ) // 1-bit input: Controls double bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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,.injectsbiterrb ( 1'b0 ) // 1-bit input: Controls single bit error injection on input data when
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// ECC enabled (Error injection capability is not available in
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// "decode_only" mode).
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,.sleep ( 1'b0 ) // 1-bit input: sleep signal to enable the dynamic power saving feature.
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);
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endmodule
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