59 lines
1.4 KiB
Systemverilog
59 lines
1.4 KiB
Systemverilog
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interface sram_if #(parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 32)(input bit clk);
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// Signals for interfacing with the SRAM
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logic [ADDR_WIDTH-1:0] addr;
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logic [DATA_WIDTH-1:0] din;
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logic [DATA_WIDTH-1:0] dout;
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logic rden;
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logic wren;
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logic [DATA_WIDTH/8-1:0] wben;
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modport master(
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output addr,
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output din,
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input dout,
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output wren,
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output rden,
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output wben
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);
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modport slave (
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input addr,
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input din,
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output dout,
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input wren,
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input rden,
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input wben
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);
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/*
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// synopsys translate_off
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// write operation
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task write;
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input logic [ADDR_WIDTH-1:0] addr_in;
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input logic [DATA_WIDTH-1:0] data_in;
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input logic [DATA_WIDTH/8-1:0] byte_enable;
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begin
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addr = addr_in;
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din = data_in;
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wben = byte_enable;
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wren = 1;
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rden = 0;
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@(posedge clk);
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wren = 0;
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end
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endtask
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// read oepration
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task read;
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input logic [ADDR_WIDTH-1:0] addr_in;
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begin
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addr = addr_in;
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wren = 0;
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rden = 1;
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@(posedge clk);
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rden = 0;
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end
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endtask
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// synopsys translate_on
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*/
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endinterface
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