91 lines
5.3 KiB
Coq
91 lines
5.3 KiB
Coq
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`include "../define/chip_define.v"
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//`define TSMC_INITIALIZE_MEM
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module dpram #(
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parameter DATAWIDTH = 32
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,parameter ADDRWIDTH = 13
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)(
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input PortClk
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,input [ADDRWIDTH-1 :0] PortAAddr
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,input [DATAWIDTH-1 :0] PortADataIn
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,input PortAWriteEnable //active low
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,input PortAChipEnable //active low
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,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
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,output [DATAWIDTH-1 :0] PortADataOut
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,input [ADDRWIDTH-1 :0] PortBAddr
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,input [DATAWIDTH-1 :0] PortBDataIn
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,input PortBWriteEnable //active low
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,input PortBChipEnable //active low
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,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
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,output [DATAWIDTH-1 :0] PortBDataOut
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);
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//==================================================================================
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//XPM¡¡£í£å£í£ï£ò£ù
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//==================================================================================
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`ifdef BEHAVIOR_SIM
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dpram_model #(
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.DATAWIDTH ( DATAWIDTH )
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,.ADDRWIDTH ( ADDRWIDTH )
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) dpram_model (
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.PortClk ( PortClk )
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,.PortAWriteEnable ( PortAWriteEnable )
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,.PortAChipEnable ( PortAChipEnable )
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,.PortAByteWriteEnable ( PortAByteWriteEnable )
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,.PortAAddr ( PortAAddr )
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,.PortADataIn ( PortADataIn )
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,.PortADataOut ( PortADataOut )
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,.PortBWriteEnable ( PortBWriteEnable )
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,.PortBChipEnable ( PortBChipEnable )
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,.PortBByteWriteEnable ( PortBByteWriteEnable_w )
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,.PortBAddr ( PortBAddr )
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,.PortBDataIn ( PortBDataIn )
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,.PortBDataOut ( PortBDataOut )
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);
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`elsif XINLINX_FPGA
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xil_tdpram #(
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.DATAWIDTH ( DATAWIDTH )
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,.ADDRWIDTH ( ADDRWIDTH )
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) U_xil_tdpram (
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.PortClk ( PortClk )
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,.PortAAddr ( PortAAddr )
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,.PortADataIn ( PortADataIn )
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,.PortAWriteEnable ( PortAWriteEnable )
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,.PortAChipEnable ( PortAChipEnable )
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,.PortAByteWriteEnable ( PortAByteWriteEnable )
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,.PortADataOut ( PortADataOut )
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,.PortBAddr ( PortBAddr )
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,.PortBDataIn ( PortBDataIn )
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,.PortBWriteEnable ( PortBWriteEnable )
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,.PortBChipEnable ( PortBChipEnable )
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,.PortBByteWriteEnable ( PortBByteWriteEnable )
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,.PortBDataOut ( PortBDataOut )
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);
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`elsif TSMC_IC
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tsmc_dpram #(
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.DATAWIDTH ( DATAWIDTH )
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,.ADDRWIDTH ( ADDRWIDTH )
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) U_tsmc_dpram (
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.PortClk ( PortClk )
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,.PortAAddr ( PortAAddr )
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,.PortADataIn ( PortADataIn )
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,.PortAWriteEnable ( PortAWriteEnable )
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,.PortAChipEnable ( PortAChipEnable )
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,.PortAByteWriteEnable ( PortAByteWriteEnable )
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,.PortADataOut ( PortADataOut )
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,.PortBAddr ( PortBAddr )
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,.PortBDataIn ( PortBDataIn )
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,.PortBWriteEnable ( PortBWriteEnable )
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,.PortBChipEnable ( PortBChipEnable )
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,.PortBByteWriteEnable ( PortBByteWriteEnable )
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,.PortBDataOut ( PortBDataOut )
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);
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`endif
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endmodule
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`include "../define/chip_undefine.v"
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