163 lines
9.7 KiB
Systemverilog
163 lines
9.7 KiB
Systemverilog
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : debug_top.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-04-13 PWY debug top-level
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// 0.2 2024-06-20 PWY dbg_sramb_wben = dbg_sram_out.wben -> dbg_sramb_wben = ~dbg_sram_out.wben
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module debug_top (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//---------------from ctrl regfile------------------------------------
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,input debug_enable //active high
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,input debug_data_sel //1'b0-->mod;1'b1-->dsp
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,input [3 :0] debug_ch_sel //2'b00-->ch0;2'b01-->ch1;2'b10-->ch2;2'b11-->ch3;
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//---------------to system regfile------------------------------------
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,output debug_update //active high
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//---------------connect mod------------------------------------------
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,input [15 :0] ch0_mod_data_i
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,input [15 :0] ch0_mod_data_q
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,input ch0_mod_vld
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,input [15 :0] ch1_mod_data_i
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,input [15 :0] ch1_mod_data_q
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,input ch1_mod_vld
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,input [15 :0] ch2_mod_data_i
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,input [15 :0] ch2_mod_data_q
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,input ch2_mod_vld
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,input [15 :0] ch3_mod_data_i
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,input [15 :0] ch3_mod_data_q
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,input ch3_mod_vld
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//---------------connect mod------------------------------------------
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,input [15 :0] ch0_dsp_data [15:0]
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,input ch0_dsp_vld
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,input [15 :0] ch1_dsp_data [15:0]
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,input ch1_dsp_vld
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,input [15 :0] ch2_dsp_data [15:0]
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,input ch2_dsp_vld
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,input [15 :0] ch3_dsp_data [15:0]
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,input ch3_dsp_vld
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//---------------connect SPI bus --------------------------------------
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,sram_if.slave dbg_sram_in
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);
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//---------------------------------------------------------------------------------------------
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//debug sampling
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//---------------------------------------------------------------------------------------------
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wire [11 :0] debug_rwaddr ;
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wire [255:0] debug_wrdata ;
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wire [31 :0] debug_bwen ;
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wire debug_wren ;
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wire debug_cen ;
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debug_sampling U_debug_sampling (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.debug_enable ( debug_enable )
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,.debug_data_sel ( debug_data_sel )
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,.debug_ch_sel ( debug_ch_sel )
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,.debug_update ( debug_update )
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,.ch0_mod_data_i ( ch0_mod_data_i )
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,.ch0_mod_data_q ( ch0_mod_data_q )
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,.ch0_mod_vld ( ch0_mod_vld )
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,.ch1_mod_data_i ( ch1_mod_data_i )
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,.ch1_mod_data_q ( ch1_mod_data_q )
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,.ch1_mod_vld ( ch1_mod_vld )
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,.ch2_mod_data_i ( ch2_mod_data_i )
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,.ch2_mod_data_q ( ch2_mod_data_q )
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,.ch2_mod_vld ( ch2_mod_vld )
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,.ch3_mod_data_i ( ch3_mod_data_i )
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,.ch3_mod_data_q ( ch3_mod_data_q )
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,.ch3_mod_vld ( ch3_mod_vld )
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,.ch0_dsp_data ( ch0_dsp_data )
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,.ch0_dsp_vld ( ch0_dsp_vld )
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,.ch1_dsp_data ( ch1_dsp_data )
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,.ch1_dsp_vld ( ch1_dsp_vld )
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,.ch2_dsp_data ( ch2_dsp_data )
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,.ch2_dsp_vld ( ch2_dsp_vld )
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,.ch3_dsp_data ( ch3_dsp_data )
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,.ch3_dsp_vld ( ch3_dsp_vld )
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,.debug_rwaddr ( debug_rwaddr )
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,.debug_wrdata ( debug_wrdata )
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,.debug_bwen ( debug_bwen )
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,.debug_wren ( debug_wren )
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,.debug_cen ( debug_cen )
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);
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//---------------------------------------------------------------------------------------------
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//debug SRAM (512w x 128d)
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//---------------------------------------------------------------------------------------------
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sram_if #(12,256) dbg_sram_out(clk);
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wire [255:0] dbg_sramb_dout ;
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wire [11 :0] dbg_sramb_addr = dbg_sram_out.addr[11:0] ;
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wire [255:0] dbg_sramb_din = dbg_sram_out.din ;
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wire [31 :0] dbg_sramb_wben = ~dbg_sram_out.wben ;
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wire dbg_sramb_wren = ~dbg_sram_out.wren & dbg_sram_out.rden ;
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wire dbg_sramb_cen = ~(dbg_sram_out.wren | dbg_sram_out.rden);
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assign dbg_sram_out.dout = dbg_sramb_dout;
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dpram #(
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.DATAWIDTH ( 256 )
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,.ADDRWIDTH ( 12 )
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) U_dbg_sram (
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.PortClk ( clk )
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,.PortAAddr ( debug_rwaddr )
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,.PortADataIn ( debug_wrdata )
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,.PortAWriteEnable ( debug_wren )
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,.PortAChipEnable ( debug_cen )
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,.PortAByteWriteEnable ( debug_bwen )
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,.PortADataOut ( )
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,.PortBAddr ( dbg_sramb_addr )
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,.PortBDataIn ( dbg_sramb_din )
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,.PortBWriteEnable ( dbg_sramb_wren )
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,.PortBChipEnable ( dbg_sramb_cen )
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,.PortBByteWriteEnable ( dbg_sramb_wben )
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,.PortBDataOut ( dbg_sramb_dout )
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);
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//---------------------------------------------------------------------------------------------
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//debug SRAM (512w x 128d)
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//---------------------------------------------------------------------------------------------
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sram_dmux_w #(
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.ADDR_WIDTH ( 12 )
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,.DATA_WIDTH_I ( 32 )
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,.DATA_WIDTH_O ( 256 )
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) U_sram_dmux_w (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.port_in ( dbg_sram_in )
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,.port_out ( dbg_sram_out )
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);
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endmodule
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