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SPI_Test/rtl/debug/debug_sample.sv

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2024-06-25 16:41:01 +08:00
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : debug_sample.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-03-13 PWY Debugging data sampling
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module debug_sampling (
//system port
input clk // System Main Clock
,input rst_n // Spi Reset active low
//---------------from ctrl regfile------------------------------------
,input debug_enable //active high
,input debug_data_sel //1'b0-->mod;1'b1-->dsp
,input [3 :0] debug_ch_sel //4'b0001-->ch0;4'b0010-->ch1;
//4'b0100-->ch2;4'b1000-->ch3;
//---------------to system regfile------------------------------------
,output debug_update //active high
//---------------connect mod------------------------------------------
,input [15 :0] ch0_mod_data_i
,input [15 :0] ch0_mod_data_q
,input ch0_mod_vld
,input [15 :0] ch1_mod_data_i
,input [15 :0] ch1_mod_data_q
,input ch1_mod_vld
,input [15 :0] ch2_mod_data_i
,input [15 :0] ch2_mod_data_q
,input ch2_mod_vld
,input [15 :0] ch3_mod_data_i
,input [15 :0] ch3_mod_data_q
,input ch3_mod_vld
//---------------connect mod------------------------------------------
,input [15 :0] ch0_dsp_data [15:0]
,input ch0_dsp_vld
,input [15 :0] ch1_dsp_data [15:0]
,input ch1_dsp_vld
,input [15 :0] ch2_dsp_data [15:0]
,input ch2_dsp_vld
,input [15 :0] ch3_dsp_data [15:0]
,input ch3_dsp_vld
//---------------debug memory mod------------------------------------------
,output [11 :0] debug_rwaddr
,output [255:0] debug_wrdata
,output [31 :0] debug_bwen
,output debug_wren
,output debug_cen
);
//
logic mod_vld;
logic dsp_vld;
//---------------addr gen----------------------------------------------------
wire end_cnt_flag;
wire [9 :0] cnt_c;
wire add_cnt = debug_enable & ((~debug_data_sel & mod_vld) | (debug_data_sel & dsp_vld)) & ~end_cnt_flag;
wire end_cnt = add_cnt & ((~debug_data_sel & cnt_c == 10'd1023) | (debug_data_sel & cnt_c ==9'd127));
wire end_cnt_flag_w = end_cnt ? 1'b1 :
~debug_enable ? 1'b0 : 1'b0;
sirv_gnrl_dfflr #(1) end_cnt_flag_dfflr ((end_cnt | ~debug_enable), end_cnt_flag_w, end_cnt_flag, clk, rst_n);
wire [9 :0] cnt_n = ~debug_enable ? 10'd0 :
end_cnt ? cnt_c :
add_cnt ? cnt_c + 1'b1 :
cnt_c ;
sirv_gnrl_dffr #(10) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n);
//---------------mod Data integration------------------------------------------
assign mod_vld = debug_ch_sel[0] & ch0_mod_vld
| debug_ch_sel[1] & ch1_mod_vld
| debug_ch_sel[2] & ch2_mod_vld
| debug_ch_sel[3] & ch3_mod_vld ;
wire [31:0] mod_data = {32{debug_ch_sel[0]}} & {ch0_mod_data_i,ch0_mod_data_q}
| {32{debug_ch_sel[1]}} & {ch1_mod_data_i,ch1_mod_data_q}
| {32{debug_ch_sel[2]}} & {ch2_mod_data_i,ch2_mod_data_q}
| {32{debug_ch_sel[3]}} & {ch3_mod_data_i,ch3_mod_data_q} ;
logic [255:0] mod_data_c;
logic [255:0] mod_data_n;
assign mod_data_n = add_cnt ? {mod_data,mod_data_c[255:32]} :
mod_data_c ;
wire [255:0] mod_wrdata = mod_data_c ;
sirv_gnrl_dffr #(256) mod_data_c_dffr (mod_data_n, mod_data_c, clk, rst_n);
//active low
wire mod_cen_w = ~((cnt_c[2:0] == 3'h7) & add_cnt);
wire mod_cen;
sirv_gnrl_dffrs #(1) mod_cen_dffrs (mod_cen_w, mod_cen, clk, rst_n);
wire [11:0] mod_addr ;
sirv_gnrl_dffr #(12) mod_addr_dffr ({cnt_c,2'b00}, mod_addr, clk, rst_n);
//---------------dsp Data integration------------------------------------------
assign dsp_vld = debug_ch_sel[0] & ch0_dsp_vld
| debug_ch_sel[1] & ch1_dsp_vld
| debug_ch_sel[2] & ch2_dsp_vld
| debug_ch_sel[3] & ch3_dsp_vld ;
wire [255:0] dsp_data = debug_ch_sel[0] ? { ch0_dsp_data[15]
,ch0_dsp_data[14]
,ch0_dsp_data[13]
,ch0_dsp_data[12]
,ch0_dsp_data[11]
,ch0_dsp_data[10]
,ch0_dsp_data[9 ]
,ch0_dsp_data[8 ]
,ch0_dsp_data[7 ]
,ch0_dsp_data[6 ]
,ch0_dsp_data[5 ]
,ch0_dsp_data[4 ]
,ch0_dsp_data[3 ]
,ch0_dsp_data[2 ]
,ch0_dsp_data[1 ]
,ch0_dsp_data[0 ]} :
debug_ch_sel[1] ? { ch1_dsp_data[15]
,ch1_dsp_data[14]
,ch1_dsp_data[13]
,ch1_dsp_data[12]
,ch1_dsp_data[11]
,ch1_dsp_data[10]
,ch1_dsp_data[9 ]
,ch1_dsp_data[8 ]
,ch1_dsp_data[7 ]
,ch1_dsp_data[6 ]
,ch1_dsp_data[5 ]
,ch1_dsp_data[4 ]
,ch1_dsp_data[3 ]
,ch1_dsp_data[2 ]
,ch1_dsp_data[1 ]
,ch1_dsp_data[0 ]} :
debug_ch_sel[2] ? { ch2_dsp_data[15]
,ch2_dsp_data[14]
,ch2_dsp_data[13]
,ch2_dsp_data[12]
,ch2_dsp_data[11]
,ch2_dsp_data[10]
,ch2_dsp_data[9 ]
,ch2_dsp_data[8 ]
,ch2_dsp_data[7 ]
,ch2_dsp_data[6 ]
,ch2_dsp_data[5 ]
,ch2_dsp_data[4 ]
,ch2_dsp_data[3 ]
,ch2_dsp_data[2 ]
,ch2_dsp_data[1 ]
,ch2_dsp_data[0 ]} :
debug_ch_sel[3] ? { ch3_dsp_data[15]
,ch3_dsp_data[14]
,ch3_dsp_data[13]
,ch3_dsp_data[12]
,ch3_dsp_data[11]
,ch3_dsp_data[10]
,ch3_dsp_data[9 ]
,ch3_dsp_data[8 ]
,ch3_dsp_data[7 ]
,ch3_dsp_data[6 ]
,ch3_dsp_data[5 ]
,ch3_dsp_data[4 ]
,ch3_dsp_data[3 ]
,ch3_dsp_data[2 ]
,ch3_dsp_data[1 ]
,ch3_dsp_data[0 ]} : 255'h0;
wire [11 :0] dsp_addr = {cnt_c[6:0],5'b00000} ;
wire dsp_cen = ~add_cnt ; //active low
wire [255:0] dsp_wrdata = dsp_data ;
////////////////////////////////////////////////////////////////////////////////////////////////////
// data & cmd mux
////////////////////////////////////////////////////////////////////////////////////////////////////
wire [11 :0] mem_addr = debug_data_sel ? dsp_addr : mod_addr ;
wire mem_cen = debug_data_sel ? dsp_cen : mod_cen ; //active low
wire [255:0] mem_wrdata = debug_data_sel ? dsp_wrdata : mod_wrdata ;
sirv_gnrl_dffr #(12) mem_addr_dffr (mem_addr, debug_rwaddr, clk, rst_n);
sirv_gnrl_dffr #(1) mem_cen_dffr (mem_cen, debug_cen, clk, rst_n);
sirv_gnrl_dffr #(256) mem_wrdata_dffr (mem_wrdata, debug_wrdata, clk, rst_n);
assign debug_bwen = 32'b0;
assign debug_wren = 1'b0;
//debug_update
sirv_gnrl_dffr #(1) debug_update_dffr (end_cnt, debug_update, clk, rst_n);
endmodule