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SPI_Test/rtl/dac_regfile/dac_regfile.v

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2024-06-25 16:41:01 +08:00
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/18 14:25:26
// Design Name:
// Module Name: dac_regfile
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// -----------------------------------------------------------
// -- Register address offset macros
// -----------------------------------------------------------
//Prbs_en Ctrl Register
`define PRBSCR 16'h0000
`define SET0CR 16'h0004
`define SET1CR 16'h0008
`define SET2CR 16'h000C
`define SET3CR 16'h0010
`define SET4CR 16'h0014
`define SET5CR 16'h0018
`define SET6CR 16'h001C
`define SET7CR 16'h0020
`define SET8CR 16'h0024
`define SET9CR 16'h0028
`define SET10CR 16'h002C
`define SET11CR 16'h0030
`define SET12CR 16'h0034
`define SET13CR 16'h0038
`define SET14CR 16'h003C
`define SET15CR 16'h0040
`define DACADDR 16'h0044
`define DACDW 16'h0048
`define DACREF 16'h004C
`define PRBSRST0 16'h0050
`define PRBSSET0 16'h0054
`define PRBSRST1 16'h0058
`define PRBSSET1 16'h005C
`define PRBSREV 16'h0060
`define CALSIG 16'h0064
`define CALEND 16'h0068
`define CALRSTN 16'h006C
`define CALDIVRSTN 16'h0070
module dac_regfile (
//system port
input clk // System Main Clock
,input rstn // Spi Reset active low
//rw op port
,input [31 :0] wrdata // write data
,input wren // write enable
,input [15 :0] rwaddr // read & write address
,input rden // read enable
,output [31 :0] rddata // read data
,output Prbs //
,output [14 :0] Set0
,output [14 :0] Set1
,output [14 :0] Set2
,output [14 :0] Set3
,output [14 :0] Set4
,output [14 :0] Set5
,output [14 :0] Set6
,output [14 :0] Set7
,output [14 :0] Set8
,output [14 :0] Set9
,output [14 :0] Set10
,output [14 :0] Set11
,output [14 :0] Set12
,output [14 :0] Set13
,output [14 :0] Set14
,output [14 :0] Set15
,output [2 :0] Dac_addr
,output [2 :0] Dac_dw
,output [8 :0] Dac_ref
,output [16 :0] Prbs_rst0
,output [16 :0] Prbs_set0
,output [16 :0] Prbs_rst1
,output [16 :0] Prbs_set1
,output Cal_sig
,input Cal_end
,output Cal_rstn
,output Cal_div_rstn
);
localparam L = 1'b0,
H = 1'b1;
// ------------------------------------------------------
// -- Register enable (select) wires
// ------------------------------------------------------
wire prbsen ; // PRBSCR select
wire set0en ;
wire set1en ;
wire set2en ;
wire set3en ;
wire set4en ;
wire set5en ;
wire set6en ;
wire set7en ;
wire set8en ;
wire set9en ;
wire set10en ;
wire set11en ;
wire set12en ;
wire set13en ;
wire set14en ;
wire set15en ;
wire dacaddren ;
wire dacdwen ;
wire dacrefen ;
wire prbsrst0en ;
wire prbsset0en ;
wire prbsrst1en ;
wire prbsset1en ;
wire prbsreven ;
wire calsigen ;
wire calenden ;
wire calrstnen ;
wire caldivrstnen ;
// ------------------------------------------------------
// -- Register write enable wires
// ------------------------------------------------------
wire prbswe ; // PRBSCR write enable
wire set0we ;
wire set1we ;
wire set2we ;
wire set3we ;
wire set4we ;
wire set5we ;
wire set6we ;
wire set7we ;
wire set8we ;
wire set9we ;
wire set10we ;
wire set11we ;
wire set12we ;
wire set13we ;
wire set14we ;
wire set15we ;
wire dacaddrwe ;
wire dacdwwe ;
wire dacrefwe ;
wire prbsrst0we ;
wire prbsset0we ;
wire prbsrst1we ;
wire prbsset1we ;
wire prbsrevwe ;
wire calsigwe ;
wire calrstnwe ;
wire caldivrstnwe ;
// ------------------------------------------------------
// -- Misc Registers
// ------------------------------------------------------
reg prbs_reg ;
reg [14 :0] set0_reg ;
reg [14 :0] set1_reg ;
reg [14 :0] set2_reg ;
reg [14 :0] set3_reg ;
reg [14 :0] set4_reg ;
reg [14 :0] set5_reg ;
reg [14 :0] set6_reg ;
reg [14 :0] set7_reg ;
reg [14 :0] set8_reg ;
reg [14 :0] set9_reg ;
reg [14 :0] set10_reg ;
reg [14 :0] set11_reg ;
reg [14 :0] set12_reg ;
reg [14 :0] set13_reg ;
reg [14 :0] set14_reg ;
reg [14 :0] set15_reg ;
reg [2 :0] dacaddr_reg ;
reg [2 :0] dacdw_reg ;
reg [8 :0] dacref_reg ;
reg [16 :0] prbsrst0_reg ;
reg [16 :0] prbsset0_reg ;
reg [16 :0] prbsrst1_reg ;
reg [16 :0] prbsset1_reg ;
reg calsig_reg ;
reg calend_reg ;
reg calrstn_reg ;
reg caldivrstn_reg ;
reg [31 :0] rddata_reg ;
// ------------------------------------------------------
// -- Address decoder
//
// Decodes the register address offset input(reg_addr)
// to produce enable (select) signals for each of the
// SW-registers in the macrocell. The reg_addr input
// is bits [8:0] of the paddr bus.
// ------------------------------------------------------
assign prbsen = (rwaddr[15:2] == `PRBSCR >> 2) ? 1'b1 : 1'b0;
assign set0en = (rwaddr[15:2] == `SET0CR >> 2) ? 1'b1 : 1'b0;
assign set1en = (rwaddr[15:2] == `SET1CR >> 2) ? 1'b1 : 1'b0;
assign set2en = (rwaddr[15:2] == `SET2CR >> 2) ? 1'b1 : 1'b0;
assign set3en = (rwaddr[15:2] == `SET3CR >> 2) ? 1'b1 : 1'b0;
assign set4en = (rwaddr[15:2] == `SET4CR >> 2) ? 1'b1 : 1'b0;
assign set5en = (rwaddr[15:2] == `SET5CR >> 2) ? 1'b1 : 1'b0;
assign set6en = (rwaddr[15:2] == `SET6CR >> 2) ? 1'b1 : 1'b0;
assign set7en = (rwaddr[15:2] == `SET7CR >> 2) ? 1'b1 : 1'b0;
assign set8en = (rwaddr[15:2] == `SET8CR >> 2) ? 1'b1 : 1'b0;
assign set9en = (rwaddr[15:2] == `SET9CR >> 2) ? 1'b1 : 1'b0;
assign set10en = (rwaddr[15:2] == `SET10CR >> 2) ? 1'b1 : 1'b0;
assign set11en = (rwaddr[15:2] == `SET11CR >> 2) ? 1'b1 : 1'b0;
assign set12en = (rwaddr[15:2] == `SET12CR >> 2) ? 1'b1 : 1'b0;
assign set13en = (rwaddr[15:2] == `SET13CR >> 2) ? 1'b1 : 1'b0;
assign set14en = (rwaddr[15:2] == `SET14CR >> 2) ? 1'b1 : 1'b0;
assign set15en = (rwaddr[15:2] == `SET15CR >> 2) ? 1'b1 : 1'b0;
assign dacaddren = (rwaddr[15:2] == `DACADDR >> 2) ? 1'b1 : 1'b0;
assign dacdwen = (rwaddr[15:2] == `DACDW >> 2) ? 1'b1 : 1'b0;
assign dacrefen = (rwaddr[15:2] == `DACREF >> 2) ? 1'b1 : 1'b0;
assign prbsrst0en = (rwaddr[15:2] == `PRBSRST0 >> 2) ? 1'b1 : 1'b0;
assign prbsset0en = (rwaddr[15:2] == `PRBSSET0 >> 2) ? 1'b1 : 1'b0;
assign prbsrst1en = (rwaddr[15:2] == `PRBSRST1 >> 2) ? 1'b1 : 1'b0;
assign prbsset1en = (rwaddr[15:2] == `PRBSSET1 >> 2) ? 1'b1 : 1'b0;
assign prbsreven = (rwaddr[15:2] == `PRBSREV >> 2) ? 1'b1 : 1'b0;
assign calsigen = (rwaddr[15:2] == `CALSIG >> 2) ? 1'b1 : 1'b0;
assign calenden = (rwaddr[15:2] == `CALEND >> 2) ? 1'b1 : 1'b0;
assign calrstnen = (rwaddr[15:2] == `CALRSTN >> 2) ? 1'b1 : 1'b0;
assign caldivrstnen = (rwaddr[15:2] == `CALDIVRSTN >> 2) ? 1'b1 : 1'b0;
// ------------------------------------------------------
// -- Write enable signals
//
// Write enable signals for writable SW-registers.
// The write enable for each register is the ANDed
// result of the register enable and the input reg_wren
// ------------------------------------------------------
assign prbswe = prbsen & wren;
assign set0we = set0en & wren;
assign set1we = set1en & wren;
assign set2we = set2en & wren;
assign set3we = set3en & wren;
assign set4we = set4en & wren;
assign set5we = set5en & wren;
assign set6we = set6en & wren;
assign set7we = set7en & wren;
assign set8we = set8en & wren;
assign set9we = set9en & wren;
assign set10we = set10en & wren;
assign set11we = set11en & wren;
assign set12we = set12en & wren;
assign set13we = set13en & wren;
assign set14we = set14en & wren;
assign set15we = set15en & wren;
assign dacaddrwe = dacaddren & wren;
assign dacdwwe = dacdwen & wren;
assign dacrefwe = dacrefen & wren;
assign prbsrst0we = prbsrst0en & wren;
assign prbsset0we = prbsset0en & wren;
assign prbsrst1we = prbsrst1en & wren;
assign prbsset1we = prbsset1en & wren;
assign prbsrevwe = prbsreven & wren;
assign calsigwe = calsigen & wren;
assign calrstnwe = calrstnen & wren;
assign caldivrstnwe = caldivrstnen & wren;
// ------------------------------------------------------
// -- prbs_reg Register
//
// Write prbs_reg for 'PRBS' : 32-bit register
// Register is split into the following bit fields
//
// [0] --> prbs_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : PRBS_PROC
if(rstn == L) begin
prbs_reg <= L;
end
else begin
if(prbswe == H) begin
prbs_reg <= wrdata[0];
end
else begin
prbs_reg <= prbs_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set0_reg Register
//
// Write set0_reg for 'SET0' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set0_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET0_PROC
if(rstn == L) begin
set0_reg <= 15'b100_0001_0011_1110;
end
else begin
if(set0we == H) begin
set0_reg <= wrdata[14 : 0];
end
else begin
set0_reg <= set0_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set1_reg Register
//
// Write set1_reg for 'SET1' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set1_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET1_PROC
if(rstn == L) begin
set1_reg <= 15'b011_1001_0001_0000;
end
else begin
if(set1we == H) begin
set1_reg <= wrdata[14 : 0];
end
else begin
set1_reg <= set1_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set2_reg Register
//
// Write set2_reg for 'SET2' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set2_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET2_PROC
if(rstn == L) begin
set2_reg <= 15'b111_1000_0000_1111;
end
else begin
if(set2we == H) begin
set2_reg <= wrdata[14 : 0];
end
else begin
set2_reg <= set2_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set3_reg Register
//
// Write set3_reg for 'SET3' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set3_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET3_PROC
if(rstn == L) begin
set3_reg <= 15'b000_1010_1101_0100;
end
else begin
if(set3we == H) begin
set3_reg <= wrdata[14 : 0];
end
else begin
set3_reg <= set3_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set4_reg Register
//
// Write set4_reg for 'SET4' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set4_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET4_PROC
if(rstn == L) begin
set4_reg <= 15'b000_0101_0110_1001;
end
else begin
if(set4we == H) begin
set4_reg <= wrdata[14 : 0];
end
else begin
set4_reg <= set4_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set5_reg Register
//
// Write set5_reg for 'SET5' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set5_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET5_PROC
if(rstn == L) begin
set5_reg <= 15'b110_1111_0011_0001;
end
else begin
if(set5we == H) begin
set5_reg <= wrdata[14 : 0];
end
else begin
set5_reg <= set5_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set6_reg Register
//
// Write set6_reg for 'SET6' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set6_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET6_PROC
if(rstn == L) begin
set6_reg <= 15'b101_1010_0011_1000;
end
else begin
if(set6we == H) begin
set6_reg <= wrdata[14 : 0];
end
else begin
set6_reg <= set6_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set7_reg Register
//
// Write set7_reg for 'SET7' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set7_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET7_PROC
if(rstn == L) begin
set7_reg <= 15'b101_0110_0110_0000;
end
else begin
if(set7we == H) begin
set7_reg <= wrdata[14 : 0];
end
else begin
set7_reg <= set7_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set8_reg Register
//
// Write set0_reg for 'SET8' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set8_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET8_PROC
if(rstn == L) begin
set8_reg <= 15'b100_1111_1000_0011;
end
else begin
if(set8we == H) begin
set8_reg <= wrdata[14 : 0];
end
else begin
set8_reg <= set8_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set9_reg Register
//
// Write set9_reg for 'SET0' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set9_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET9_PROC
if(rstn == L) begin
set9_reg <= 15'b010_1110_1001_0101;
end
else begin
if(set9we == H) begin
set9_reg <= wrdata[14 : 0];
end
else begin
set9_reg <= set9_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set10_reg Register
//
// Write set10_reg for 'SET10' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set10_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET10_PROC
if(rstn == L) begin
set10_reg <= 15'b101_0100_0001_0111;
end
else begin
if(set10we == H) begin
set10_reg <= wrdata[14 : 0];
end
else begin
set10_reg <= set10_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set11_reg Register
//
// Write set11_reg for 'SET11' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set11_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET11_PROC
if(rstn == L) begin
set11_reg <= 15'b001_0110_1101_1110;
end
else begin
if(set11we == H) begin
set11_reg <= wrdata[14 : 0];
end
else begin
set11_reg <= set11_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set12_reg Register
//
// Write set12_reg for 'SET12' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set12_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET12_PROC
if(rstn == L) begin
set12_reg <= 15'b000_1110_1110_1001;
end
else begin
if(set12we == H) begin
set12_reg <= wrdata[14 : 0];
end
else begin
set12_reg <= set12_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set13_reg Register
//
// Write set13_reg for 'SET13' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set13_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET13_PROC
if(rstn == L) begin
set13_reg <= 15'b001_0110_1001_1100;
end
else begin
if(set13we == H) begin
set13_reg <= wrdata[14 : 0];
end
else begin
set13_reg <= set13_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set14_reg Register
//
// Write set14_reg for 'SET14' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set14_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET14_PROC
if(rstn == L) begin
set14_reg <= 15'b001_0001_0011_0101;
end
else begin
if(set14we == H) begin
set14_reg <= wrdata[14 : 0];
end
else begin
set14_reg <= set14_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- set15_reg Register
//
// Write set15_reg for 'SET15' : 32-bit register
// Register is split into the following bit fields
//
// [14 : 0] --> set15_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : SET15_PROC
if(rstn == L) begin
set15_reg <= 15'b101_1101_1101_0001;
end
else begin
if(set15we == H) begin
set15_reg <= wrdata[14 : 0];
end
else begin
set15_reg <= set15_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- dacaddr_reg Register
//
// Write dacaddr_reg for 'DACADDR' : 32-bit register
// Register is split into the following bit fields
//
// [2 : 0] --> dacaddr_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : DACADDR_PROC
if(rstn == L) begin
dacaddr_reg <= 3'b000;
end
else begin
if(dacaddrwe == H) begin
dacaddr_reg <= wrdata[2 : 0];
end
else begin
dacaddr_reg <= dacaddr_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- dacdw_reg Register
//
// Write dacdw_reg for 'DACDW' : 32-bit register
// Register is split into the following bit fields
//
// [2 : 0] --> dacdw_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : DACDW_PROC
if(rstn == L) begin
dacdw_reg <= 3'b000;
end
else begin
if(dacdwwe == H) begin
dacdw_reg <= wrdata[2 : 0];
end
else begin
dacdw_reg <= dacdw_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- dacref_reg Register
//
// Write dacref_reg for 'DACREF' : 32-bit register
// Register is split into the following bit fields
//
// [8 : 0] --> dacref_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : DACREF_PROC
if(rstn == L) begin
dacref_reg <= 9'b0_1000_1000;
end
else begin
if(dacrefwe == H) begin
dacref_reg <= wrdata[8 : 0];
end
else begin
dacref_reg <= dacref_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- prbsrst0_reg Register
//
// Write prbsrst0_reg for 'PRBSRST0' : 32-bit register
// Register is split into the following bit fields
//
// [16 : 0] --> prbsrst0_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : PRBSRST0_PROC
if(rstn == L) begin
prbsrst0_reg <= 17'b0_0000_0001_1111_1111;
end
else begin
if(prbsrst0we == H) begin
prbsrst0_reg <= wrdata[16 : 0];
end
else if(prbsrevwe) begin
prbsrst0_reg <= 17'b0_0000_0000_0000_0000;
end
else begin
prbsrst0_reg <= prbsrst0_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- prbsset0_reg Register
//
// Write prbsset0_reg for 'PRBSRST0' : 32-bit register
// Register is split into the following bit fields
//
// [16 : 0] --> prbsset0_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : PRBSSET0_PROC
if(rstn == L) begin
prbsset0_reg <= 17'b1_1111_1110_0000_0000;
end
else begin
if(prbsset0we == H) begin
prbsset0_reg <= wrdata[16 : 0];
end
else if(prbsrevwe) begin
prbsset0_reg <= 17'b0_0000_0000_0000_0000;
end
else begin
prbsset0_reg <= prbsset0_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- prbsrst1_reg Register
//
// Write prbsrst1_reg for 'PRBSRST1' : 32-bit register
// Register is split into the following bit fields
//
// [16 : 0] --> prbsrst1_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : PRBSRST1_PROC
if(rstn == L) begin
prbsrst1_reg <= 17'b0_0000_0000_1111_1111;
end
else begin
if(prbsrst1we == H) begin
prbsrst1_reg <= wrdata[16 : 0];
end
else if(prbsrevwe) begin
prbsrst1_reg <= 17'b0_0000_0000_0000_0000;
end
else begin
prbsrst1_reg <= prbsrst1_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- prbsset1_reg Register
//
// Write prbsset1_reg for 'PRBSRST1' : 32-bit register
// Register is split into the following bit fields
//
// [16 : 0] --> prbsset1_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : PRBSSET1_PROC
if(rstn == L) begin
prbsset1_reg <= 17'b1_1111_1111_0000_0000;
end
else begin
if(prbsset1we == H) begin
prbsset1_reg <= wrdata[16 : 0];
end
else if(prbsrevwe) begin
prbsset1_reg <= 17'b0_0000_0000_0000_0000;
end
else begin
prbsset1_reg <= prbsset1_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- calsig_reg Register
//
// Write calsig_reg for 'CALSIG' : 32-bit register
// Register is split into the following bit fields
//
// [0] --> calsig_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : CALSIG_PROC
if(rstn == L) begin
calsig_reg <= 1'b0;
end
else begin
if(calsigwe == H) begin
calsig_reg <= wrdata[0];
end
else begin
calsig_reg <= calsig_reg; // hold current value
end
end
end
// ------------------------------------------------------
// -- calend_reg Register
//
// Write calend_reg for 'CALEND' : 32-bit register
// Register is split into the following bit fields
//
// [0] --> calend_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : CALEND_PROC
if(rstn == L) begin
calend_reg <= 1'b0;
end
else begin
calend_reg <= Cal_end;
end
end
// ------------------------------------------------------
// -- calrstn_reg Register
//
// Write calrstn_reg for 'CALRSTN' : 32-bit register
// Register is split into the following bit fields
//
// [0] --> calrstn_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : CALRSTN_PROC
if(rstn == L) begin
calrstn_reg <= 1'b0;
end
else if(calrstnwe) begin
calrstn_reg <= wrdata[0];
end
else begin
calrstn_reg <= calrstn_reg;
end
end
// ------------------------------------------------------
// -- caldivrstn_reg Register
//
// Write caldivrstn_reg for 'CALDIVRSTN' : 32-bit register
// Register is split into the following bit fields
//
// [0] --> caldivrstn_reg
// ------------------------------------------------------
always @(posedge clk or negedge rstn) begin : CALDIVRSTN_PROC
if(rstn == L) begin
caldivrstn_reg <= 1'b1;
end
else if(caldivrstnwe) begin
caldivrstn_reg <= wrdata[0];
end
else begin
caldivrstn_reg <= caldivrstn_reg;
end
end
// ------------------------------------------------------
// -- Read data mux
//
// -- The data from the selected register is
// -- placed on a zero-padded 32-bit read data bus.
// ------------------------------------------------------
always @(*) begin : RDDATA_PROC
rddata_reg = {32{1'b0}};
if(prbsen == H ) rddata_reg[0 ] = prbs_reg ;
if(set0en == H ) rddata_reg[14:0] = set0_reg ;
if(set1en == H ) rddata_reg[14:0] = set1_reg ;
if(set2en == H ) rddata_reg[14:0] = set2_reg ;
if(set3en == H ) rddata_reg[14:0] = set3_reg ;
if(set4en == H ) rddata_reg[14:0] = set4_reg ;
if(set5en == H ) rddata_reg[14:0] = set5_reg ;
if(set6en == H ) rddata_reg[14:0] = set6_reg ;
if(set7en == H ) rddata_reg[14:0] = set7_reg ;
if(set8en == H ) rddata_reg[14:0] = set8_reg ;
if(set9en == H ) rddata_reg[14:0] = set9_reg ;
if(set10en == H ) rddata_reg[14:0] = set10_reg ;
if(set11en == H ) rddata_reg[14:0] = set11_reg ;
if(set12en == H ) rddata_reg[14:0] = set12_reg ;
if(set13en == H ) rddata_reg[14:0] = set13_reg ;
if(set14en == H ) rddata_reg[14:0] = set14_reg ;
if(set15en == H ) rddata_reg[14:0] = set15_reg ;
if(dacaddren == H ) rddata_reg[2 :0] = dacaddr_reg ;
if(dacdwen == H ) rddata_reg[2 :0] = dacdw_reg ;
if(dacrefen == H ) rddata_reg[8 :0] = dacref_reg ;
if(prbsrst0en == H ) rddata_reg[16:0] = prbsrst0_reg ;
if(prbsset0en == H ) rddata_reg[16:0] = prbsset0_reg ;
if(prbsrst1en == H ) rddata_reg[16:0] = prbsrst1_reg ;
if(prbsset1en == H ) rddata_reg[16:0] = prbsset1_reg ;
if(calsigen == H ) rddata_reg[0 ] = calsig_reg ;
if(calenden == H ) rddata_reg[0 ] = calend_reg ;
if(calrstnen == H ) rddata_reg[0 ] = calrstn_reg ;
if(caldivrstnen == H ) rddata_reg[0 ] = caldivrstn_reg ;
end
//rddata
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rstn);
// ------------------------------------------------------
// -- Output signals assignment
// ------------------------------------------------------
assign Prbs = prbs_reg ;
assign Set0 = set0_reg ;
assign Set1 = set1_reg ;
assign Set2 = set2_reg ;
assign Set3 = set3_reg ;
assign Set4 = set4_reg ;
assign Set5 = set5_reg ;
assign Set6 = set6_reg ;
assign Set7 = set7_reg ;
assign Set8 = set8_reg ;
assign Set9 = set9_reg ;
assign Set10 = set10_reg ;
assign Set11 = set11_reg ;
assign Set12 = set12_reg ;
assign Set13 = set13_reg ;
assign Set14 = set14_reg ;
assign Set15 = set15_reg ;
assign Dac_addr = dacaddr_reg ;
assign Dac_dw = dacdw_reg ;
assign Dac_ref = dacref_reg ;
assign Prbs_rst0 = prbsrst0_reg ;
assign Prbs_set0 = prbsset0_reg ;
assign Prbs_rst1 = prbsrst1_reg ;
assign Prbs_set1 = prbsset1_reg ;
assign Cal_sig = calsig_reg ;
assign Cal_rstn = calrstn_reg ;
assign Cal_div_rstn = caldivrstn_reg ;
endmodule
`undef PRBSCR
`undef SET0CR
`undef SET1CR
`undef SET2CR
`undef SET3CR
`undef SET4CR
`undef SET5CR
`undef SET6CR
`undef SET7CR
`undef SET8CR
`undef SET9CR
`undef SET10CR
`undef SET11CR
`undef SET12CR
`undef SET13CR
`undef SET14CR
`undef SET15CR
`undef DACADDR
`undef DACDW
`undef DACREF
`undef PRBSRST0
`undef PRBSSET0
`undef PRBSRST1
`undef PRBSSET1
`undef PRBSREV
`undef CALSIG
`undef CALEND
`undef CALRSTN
`undef CALDIVRSTN