84 lines
2.9 KiB
Systemverilog
84 lines
2.9 KiB
Systemverilog
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : awg_ctrl.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY Configuration parameters lookup tabl
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module param_lut (
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clk
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,rst_n
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,param_i
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,index_i
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,index_vld_i
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,param_o
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);
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//=================================================
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function integer clog2(input integer depth);
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begin
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for(clog2=0;depth>1;clog2=clog2+1)
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depth =depth>>1;
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end
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endfunction
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//=================================================
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parameter DXLEN = 32;
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parameter PNUM = 4;
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//=================================================
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//system port
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input clk ;
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input rst_n ;
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input [DXLEN-1 :0] param_i [PNUM-1:0] ;
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input [clog2(PNUM)-1 :0] index_i ;
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input index_vld_i ;
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output [DXLEN-1 :0] param_o ;
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generate
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genvar i;
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wire [PNUM-1 :0] cs_slv;
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wire [DXLEN-1 :0] dtemp [PNUM-1:0];
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for(i=0;i<PNUM;i=i+1) begin: CS_SLV
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assign cs_slv[i] = (index_i == i );
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if(i==0)begin: DTEMP0
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assign dtemp[i] = (cs_slv[i]) ? param_i[i] : 32'b0;
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end
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else begin: DTEMP1_32
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assign dtemp[i] = (cs_slv[i]) ? param_i[i] : dtemp[i-1];
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end
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end
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endgenerate
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//paramter register
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sirv_gnrl_dfflr #(DXLEN) param_dfflr (index_vld_i, dtemp[PNUM-1], param_o, clk, rst_n);
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endmodule
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