66 lines
2.8 KiB
Coq
66 lines
2.8 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : modout_mux.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-05-13 PWY debug top-level
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module modout_mux (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//---------------from ctrl regfile------------------------------------
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,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
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//mod nco data
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,input [15:0] sin
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,input [15:0] cos
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//mod modem data
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,input [15:0] mod_data_i
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,input [15:0] mod_data_q
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,input mod_data_vld
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//mux out data
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,output [15:0] mux_data_i
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,output [15:0] mux_data_q
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,output mux_data_vld
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);
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wire [15:0] mux_data_i_w = sel ? sin : mod_data_i;
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wire [15:0] mux_data_q_w = sel ? cos : mod_data_q;
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wire mux_data_vld_w = sel ? 1'b1 : mod_data_vld;
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`ifdef MODDOUT_MUX_REG
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sirv_gnrl_dffr #(16) mux_data_i_dffr (mux_data_i_w , mux_data_i , clk, rst_n);
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sirv_gnrl_dffr #(16) mux_data_q_dffr (mux_data_q_w , mux_data_q , clk, rst_n);
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sirv_gnrl_dffr #(1 ) mux_data_vld_dffr (mux_data_vld_w, mux_data_vld, clk, rst_n);
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`else
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assign mux_data_i = mux_data_i_w ;
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assign mux_data_q = mux_data_q_w ;
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assign mux_data_vld = mux_data_vld_w ;
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`endif
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endmodule
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