594 lines
26 KiB
Coq
594 lines
26 KiB
Coq
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : ctrl_regfile.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY AWG dedicated register file
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// 0.2 2024-05-13 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//MCU parameter register 0
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`define MCUPARAR0 16'h00
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//MCU parameter register 1
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`define MCUPARAR1 16'h04
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//MCU parameter register 2
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`define MCUPARAR2 16'h08
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//MCU parameter register 3
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`define MCUPARAR3 16'h0C
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//MCU result register 0
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`define MCURESR0 16'h10
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//MCU result register 1
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`define MCURESR1 16'h14
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//MCU result register 2
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`define MCURESR2 16'h18
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//MCU result register 3
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`define MCURESR3 16'h1C
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//Run-time register
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`define RTIMR 16'h98
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//Instruction count register
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`define ICNTR 16'h9C
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//Feedback state information register
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`define FSIR 16'hA0
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//Modulator Operation Mode Register
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`define MODMR 16'h100
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//Interpolator Operation Mode Register
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`define INTPMR 16'h104
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//Frequency Mixer NCO Clear Register
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`define MIXNCOCR 16'h108
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//Frequency Mixer NCO Frequency Control Word High 32-bit Register
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`define MIXNFCWHR 16'h10C
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//Frequency Mixer NCO Frequency Control Word Low 16-bit Register
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`define MIXNFCWLR 16'h110
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//Frequency Mixer NCO Phase Control Word Register
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`define MIXNPHAR 16'h114
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//Frequency Mixer Operating Mode Register
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`define MIXMR 16'h118
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//Frequency Mixer Output Data Type Register
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`define MIXODTR 16'h11C
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//Frequency Mixer Output Data Format Register
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`define MIXODFR 16'h120
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//Roler Selection Register
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`define ROLER 16'h128
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//Mixed-frequency NCO sync clear enable Register
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`define MIXNCOSCER 16'h12C
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//AWG data out type select Register
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`define MODDOTR 16'h130
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//Status Register
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`define STR 16'h134
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//AWG always on Register
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`define DSPAOR 16'h138
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module ctrl_regfile (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [15 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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,input [1 :0] fb_st_i
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,input [31 :0] run_time
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,input [31 :0] instr_num
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,input bais_i_ov
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,input bais_q_ov
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,input awg_ctrl_fsm_st
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//MCU and SPI interface for interaction
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,output [31 :0] mcu_param0 // MCU parameter 0
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,output [31 :0] mcu_param1 // MCU parameter 1
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,output [31 :0] mcu_param2 // MCU parameter 2
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,output [31 :0] mcu_param3 // MCU parameter 3
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,input [31 :0] mcu_result0 // MCU result 0
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,input [31 :0] mcu_result1 // MCU result 1
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,input [31 :0] mcu_result2 // MCU result 2
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,input [31 :0] mcu_result3 // MCU result 3
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,output [1 :0] fb_st_o
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//awg cfg
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,output mod_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
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//DSP cfg
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,output qam_nco_clr
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,output qam_nco_sclr_en
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,output [47 :0] qam_fcw////////////////////////////////////////////////////////////////////////////////////////////////////
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,output [15 :0] qam_pha //////////////////////////////////////////////////////////////////////////////////////////////
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,output [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
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//2'b10:cos;2'b11:sin;
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,output qam_sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband;
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,output [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;
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//3'b011:x8;3'b100:x16;
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,output [1 :0] role_sel //[0] --> 1'b0: xy-chip;1'b1: z-chip;
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//[1] --> 1'b0:AC mode;1'b1: DC mode;
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//Please note that when the role is set to xy-chip,
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//only AC mode is supported.
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,output [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode;
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//2'b10:2xNRZ mode;2'b00:reserve;
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,output dout_sel //1'b0 --> mod modem data; 1'b1 --> mod nco data
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//1'b0 --> Z dsp data for ZDAC; 1'b1 --> xy dsp data for ZDAC
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,output dsp_alwayson //1'b0 --> dsp output data vaild depend on awg vaild;
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//1'b1 --> dsp output data always vaild;
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);
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localparam L = 1'b0,
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H = 1'b1;
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire mcuparar0en ; // MCUPARAR0 select
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wire mcuparar1en ; // MCUPARAR1 select
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wire mcuparar2en ; // MCUPARAR2 select
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wire mcuparar3en ; // MCUPARAR3 select
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wire mcuresr0en ; // MCURESR0 select
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wire mcuresr1en ; // MCURESR1 select
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wire mcuresr2en ; // MCURESR2 select
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wire mcuresr3en ; // MCURESR3 select
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wire rtimren ; // RTIMR select
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wire icntren ; // ICNTR select
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wire fsiren ; // FSIR select
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wire modmren ; // MODMR select
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wire intpmren ; // INTPMR select
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wire mixncocren ; // MIXNCOCR select
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wire mixnfcwhren ; // MIXNFCWHR select
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wire mixnfcwlren ; // MIXNFCWLR select
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wire mixnpharen ; // MIXNPHAR select
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wire mixmren ; // MIXMR select
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wire mixodtren ; // MIXODTR select
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wire mixodfren ; // MIXODFR select
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wire roleren ; // ROLER select
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wire mixncosceren ; // MIXNCOSCER select
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wire stren ; // BAISOVR select
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wire moddotren ; // MODDOTR select
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wire dspaoren ; // DSPAOR select
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire mcuparar0we ; // MCUPARAR0 write enable
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wire mcuparar1we ; // MCUPARAR1 write enable
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wire mcuparar2we ; // MCUPARAR2 write enable
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wire mcuparar3we ; // MCUPARAR3 write enable
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wire modmrwe ; // MODMR write enable
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wire intpmrwe ; // INTPMR write enable
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wire mixncocrwe ; // MIXNCOCR write enable
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wire mixnfcwhrwe ; // MIXNFCWHR write enable
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wire mixnfcwlrwe ; // MIXNFCWLR write enable
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wire mixnpharwe ; // MIXNPHAR write enable
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wire mixmrwe ; // MIXMR write enable
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wire mixodtrwe ; // MIXODTR write enable
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wire mixodfrwe ; // MIXODFR write enable
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wire rolerwe ; // ROLER write enable
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wire mixncoscerwe ; // MIXNCOSCER write enable
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wire moddotrwe ; // MODDOTR write enable
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wire dspaorwe ; // DSPAOR write enable
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// ------------------------------------------------------
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// -- Misc wires
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// ------------------------------------------------------
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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wire [31 :0] mcuparar0 ; // MCUPARAR0 register
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wire [31 :0] mcuparar1 ; // MCUPARAR1 register
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wire [31 :0] mcuparar2 ; // MCUPARAR2 register
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wire [31 :0] mcuparar3 ; // MCUPARAR3 register
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wire [31 :0] mcuresr0 ; // MCURESR0 register
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wire [31 :0] mcuresr1 ; // MCURESR1 register
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wire [31 :0] mcuresr2 ; // MCURESR2 register
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wire [31 :0] mcuresr3 ; // MCURESR3 register
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wire [31 :0] rtimr ; // RTIMR register
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wire [31 :0] icntr ; // ICNTR register
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wire [1 :0] fsir ; // FSIR register
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wire [0 :0] modmr ; // MODMR register
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wire [2 :0] intpmr ; // INTPMR register
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wire [0 :0] mixncocr ; // MIXNCOCR register
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wire [31 :0] mixnfcwhr ; // MIXNFCWHR register
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wire [15 :0] mixnfcwlr ; // MIXNFCWLR register
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wire [15 :0] mixnphar ; // MIXNPHAR register
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wire [0 :0] mixmr ; // MIXMR register
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wire [1 :0] mixodtr ; // MIXODTR register
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wire [1 :0] mixodfr ; // MIXODFR register
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wire [1 :0] roler ; // ROLER register
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wire [0 :0] dspaor ; // DSPAOR register
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wire [0 :0] mixncoscer ; // MIXNCOSCER register
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wire moddotr ; // MODDOTR register
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reg [31: 0] rddata_reg ;
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// ------------------------------------------------------
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// -- Address decoder
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//
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// Decodes the register address offset input(reg_addr)
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// to produce enable (select) signals for each of the
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// SW-registers in the macrocell. The reg_addr input
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// is bits [15:0] of the paddr bus.
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// ------------------------------------------------------
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assign mcuparar0en = (rwaddr[15:2] == `MCUPARAR0 >> 2) ? 1'b1 : 1'b0;
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assign mcuparar1en = (rwaddr[15:2] == `MCUPARAR1 >> 2) ? 1'b1 : 1'b0;
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assign mcuparar2en = (rwaddr[15:2] == `MCUPARAR2 >> 2) ? 1'b1 : 1'b0;
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assign mcuparar3en = (rwaddr[15:2] == `MCUPARAR3 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr0en = (rwaddr[15:2] == `MCURESR0 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr1en = (rwaddr[15:2] == `MCURESR1 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr2en = (rwaddr[15:2] == `MCURESR2 >> 2) ? 1'b1 : 1'b0;
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assign mcuresr3en = (rwaddr[15:2] == `MCURESR3 >> 2) ? 1'b1 : 1'b0;
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assign rtimren = (rwaddr[15:2] == `RTIMR >> 2) ? 1'b1 : 1'b0;
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assign icntren = (rwaddr[15:2] == `ICNTR >> 2) ? 1'b1 : 1'b0;
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assign fsiren = (rwaddr[15:2] == `FSIR >> 2) ? 1'b1 : 1'b0;
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assign modmren = (rwaddr[15:2] == `MODMR >> 2) ? 1'b1 : 1'b0;
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assign intpmren = (rwaddr[15:2] == `INTPMR >> 2) ? 1'b1 : 1'b0;
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assign mixncocren = (rwaddr[15:2] == `MIXNCOCR >> 2) ? 1'b1 : 1'b0;
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assign mixnfcwhren = (rwaddr[15:2] == `MIXNFCWHR >> 2) ? 1'b1 : 1'b0;
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assign mixnfcwlren = (rwaddr[15:2] == `MIXNFCWLR >> 2) ? 1'b1 : 1'b0;
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assign mixnpharen = (rwaddr[15:2] == `MIXNPHAR >> 2) ? 1'b1 : 1'b0;
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assign mixmren = (rwaddr[15:2] == `MIXMR >> 2) ? 1'b1 : 1'b0;
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assign mixodtren = (rwaddr[15:2] == `MIXODTR >> 2) ? 1'b1 : 1'b0;
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assign mixodfren = (rwaddr[15:2] == `MIXODFR >> 2) ? 1'b1 : 1'b0;
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assign roleren = (rwaddr[15:2] == `ROLER >> 2) ? 1'b1 : 1'b0;
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assign mixncosceren = (rwaddr[15:2] == `MIXNCOSCER >> 2) ? 1'b1 : 1'b0;
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assign stren = (rwaddr[15:2] == `STR >> 2) ? 1'b1 : 1'b0;
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assign moddotren = (rwaddr[15:2] == `MODDOTR >> 2) ? 1'b1 : 1'b0;
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assign dspaoren = (rwaddr[15:2] == `DSPAOR >> 2) ? 1'b1 : 1'b0;
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// ------------------------------------------------------
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// -- Write enable signals
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//
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// Write enable signals for writable SW-registers.
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// The write enable for each register is the ANDed
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// result of the register enable and the input reg_wren
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// ------------------------------------------------------
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assign mcuparar0we = mcuparar0en & wren;
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assign mcuparar1we = mcuparar1en & wren;
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assign mcuparar2we = mcuparar2en & wren;
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assign mcuparar3we = mcuparar3en & wren;
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assign modmrwe = modmren & wren;///////////
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assign intpmrwe = intpmren & wren;
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assign mixncocrwe = mixncocren & wren;
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assign mixnfcwhrwe = mixnfcwhren & wren;
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assign mixnfcwlrwe = mixnfcwlren & wren;
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assign mixnpharwe = mixnpharen & wren;
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assign mixmrwe = mixmren & wren;
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assign mixodtrwe = mixodtren & wren;
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assign mixodfrwe = mixodfren & wren;
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assign rolerwe = roleren & wren;
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assign mixncoscerwe = mixncosceren & wren;
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assign moddotrwe = moddotren & wren;
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assign dspaorwe = dspaoren & wren;
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// ------------------------------------------------------
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// -- mcuparar0 register
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//
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// Write mcuparar0 for 'MCUPARAR0' : 32-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> mcuparar0
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// ------------------------------------------------------
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sirv_gnrl_dfflr #(32) mcuparar0_dfflr (mcuparar0we, wrdata[31:0], mcuparar0, clk, rst_n);
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// ------------------------------------------------------
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// -- mcuparar1 register
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//
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// Write mcuparar1 for 'MCUPARAR1' : 32-bit register
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// Register is split into the following bit fields
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//
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// [31:0] --> mcuparar1
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// ------------------------------------------------------
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sirv_gnrl_dfflr #(32) mcuparar1_dfflr (mcuparar1we, wrdata[31:0], mcuparar1, clk, rst_n);
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// ------------------------------------------------------
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// -- mcuparar2 register
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//
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// Write mcuparar2 for 'MCUPARAR2' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuparar2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mcuparar2_dfflr (mcuparar2we, wrdata[31:0], mcuparar2, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuparar3 register
|
||
|
|
//
|
||
|
|
// Write mcuparar3 for 'MCUPARAR3' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mcuparar3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mcuparar3_dfflr (mcuparar3we, wrdata[31:0], mcuparar3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- modmr register
|
||
|
|
//
|
||
|
|
// Write modmr for 'MODMR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> modmr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) modmr_dfflr (modmrwe, wrdata[0], modmr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- intpmr register
|
||
|
|
//
|
||
|
|
// Write intpmr for 'INTPMR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [2:0] --> intpmr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(3) intpmr_dfflr (intpmrwe, wrdata[2:0], intpmr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixncocr register
|
||
|
|
//
|
||
|
|
// Write mixncocr for 'MIXNCOCR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> mixncocr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) mixncocr_dfflr (mixncocrwe, wrdata[0], mixncocr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixnfcwhr register
|
||
|
|
//
|
||
|
|
// Write mixnfcwhr for 'MIXNFCWHR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:0] --> mixnfcwhr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(32) mixnfcwhr_dfflr (mixnfcwhrwe, wrdata[31:0], mixnfcwhr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixnfcwlr register
|
||
|
|
//
|
||
|
|
// Write mixnfcwlr for 'MIXNFCWHR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> mixnfcwlr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(16) mixnfcwlr_dfflr (mixnfcwlrwe, wrdata[31:16], mixnfcwlr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixnphar register
|
||
|
|
//
|
||
|
|
// Write mixnphar for 'MIXNPHAR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [31:16] --> mixnphar
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(16) mixnphar_dfflr (mixnpharwe, wrdata[31:16], mixnphar, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixmr register
|
||
|
|
//
|
||
|
|
// Write mixmr for 'MIXNPHAR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> mixmr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) mixmr_dfflr (mixmrwe, wrdata[0], mixmr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixodtr register
|
||
|
|
//
|
||
|
|
// Write mixodtr for 'MIXNPHAR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1:0] --> mixodtr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(2) mixodtr_dfflr (mixodtrwe, wrdata[1:0], mixodtr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixodfr register
|
||
|
|
//
|
||
|
|
// Write mixodfr for 'MIXODFR' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1:0] --> mixodfr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(2) mixodfr_dfflr (mixodfrwe, wrdata[1:0], mixodfr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- roler register
|
||
|
|
//
|
||
|
|
// Write roler for 'ROLER' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [1] --> AC or DC mode select
|
||
|
|
// [0] --> xy-chip or z-chip select
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) roler0_dfflr (rolerwe, wrdata[0], roler[0], clk, rst_n);
|
||
|
|
|
||
|
|
//Please note that when the role is set to xy-chip, only AC mode is supported.
|
||
|
|
wire mode_w = wrdata[0] & wrdata[1];
|
||
|
|
// 0 | 0 | x
|
||
|
|
// 0 | 1 | 0
|
||
|
|
// 1 | 1 | 1
|
||
|
|
|
||
|
|
sirv_gnrl_dfflr #(1) roler1_dfflr (rolerwe, mode_w, roler[1], clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mixncoscer register
|
||
|
|
//
|
||
|
|
// Write mixncoscer for 'mixncoscer' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> mixncoscer
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) mixncoscer_dfflr (mixncoscerwe, wrdata[0], mixncoscer, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- moddotr register
|
||
|
|
//
|
||
|
|
// Write moddotr for 'moddotr' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> moddotr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflr #(1) moddotr_dfflr (moddotrwe, wrdata[0], moddotr, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- dspaor register
|
||
|
|
//
|
||
|
|
// Write dspaor for 'dspaor' : 32-bit register
|
||
|
|
// Register is split into the following bit fields
|
||
|
|
//
|
||
|
|
// [0] --> dspaor
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dfflrs #(1) dspaor_dfflrs (dspaorwe, wrdata[0], dspaor, clk, rst_n);
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr0
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar0_dffr (mcu_result0, mcuresr0, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr1
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar1_dffr (mcu_result1, mcuresr1, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr2
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar2_dffr (mcu_result2, mcuresr2, clk, rst_n);
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- mcuresr3
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) mcuparar3_dffr (mcu_result3, mcuresr3, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- rtimr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) rtimr_dffr (run_time, rtimr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- icntr
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(32) icntr_dffr (instr_num, icntr, clk, rst_n);
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- fsir
|
||
|
|
// ------------------------------------------------------
|
||
|
|
sirv_gnrl_dffr #(2) fsir_dffr (fb_st_i[1:0], fsir, clk, rst_n);//////////////////////////////////////////////////////////[1:0]
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Read data mux
|
||
|
|
//
|
||
|
|
// -- The data from the selected register is
|
||
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
||
|
|
// ------------------------------------------------------
|
||
|
|
always @(*) begin : RDDATA_PROC
|
||
|
|
rddata_reg = {32{1'b0}};
|
||
|
|
if(mcuparar0en == H ) rddata_reg[31:0] = mcuparar0 ;
|
||
|
|
if(mcuparar1en == H ) rddata_reg[31:0] = mcuparar1 ;
|
||
|
|
if(mcuparar2en == H ) rddata_reg[31:0] = mcuparar2 ;
|
||
|
|
if(mcuparar3en == H ) rddata_reg[31:0] = mcuparar3 ;
|
||
|
|
if(mcuresr0en == H ) rddata_reg[31:0] = mcuresr0 ;
|
||
|
|
if(mcuresr1en == H ) rddata_reg[31:0] = mcuresr1 ;
|
||
|
|
if(mcuresr2en == H ) rddata_reg[31:0] = mcuresr2 ;
|
||
|
|
if(mcuresr3en == H ) rddata_reg[31:0] = mcuresr3 ;
|
||
|
|
if(rtimren == H ) rddata_reg[31:0] = rtimr ;
|
||
|
|
if(icntren == H ) rddata_reg[31:0] = icntr ;
|
||
|
|
if(fsiren == H ) rddata_reg[1 :0] = fsir ;
|
||
|
|
if(modmren == H ) rddata_reg[0 :0] = modmr ;
|
||
|
|
if(intpmren == H ) rddata_reg[2 :0] = intpmr ;
|
||
|
|
if(roleren == H ) rddata_reg[1 :0] = roler ;
|
||
|
|
if(mixncocren == H ) rddata_reg[0 :0] = mixncocr ;
|
||
|
|
if(mixnfcwhren == H ) rddata_reg[31:0] = mixnfcwhr ;
|
||
|
|
if(mixnfcwlren == H ) rddata_reg[15:0] = mixnfcwlr ;
|
||
|
|
if(mixnpharen == H ) rddata_reg[15:0] = mixnphar ;
|
||
|
|
if(mixmren == H ) rddata_reg[0 :0] = mixmr ;
|
||
|
|
if(mixodtren == H ) rddata_reg[1 :0] = mixodtr ;
|
||
|
|
if(mixodfren == H ) rddata_reg[1 :0] = mixodfr ;
|
||
|
|
if(mixncosceren == H ) rddata_reg[0 :0] = mixncoscer ;
|
||
|
|
if(moddotren == H ) rddata_reg[0 :0] = moddotr ;
|
||
|
|
if(stren == H ) rddata_reg[2 :0] = {bais_q_ov,bais_i_ov,awg_ctrl_fsm_st} ;
|
||
|
|
if(dspaoren == H ) rddata_reg[0 :0] = dspaor ;
|
||
|
|
end
|
||
|
|
|
||
|
|
// ------------------------------------------------------
|
||
|
|
// -- Output signals assignment
|
||
|
|
// ------------------------------------------------------
|
||
|
|
|
||
|
|
//mcu result
|
||
|
|
assign mcu_param0 = mcuparar0 ;
|
||
|
|
assign mcu_param1 = mcuparar1 ;
|
||
|
|
assign mcu_param2 = mcuparar2 ;
|
||
|
|
assign mcu_param3 = mcuparar3 ;
|
||
|
|
|
||
|
|
//fb_st_o
|
||
|
|
assign fb_st_o = fsir ;
|
||
|
|
//awg cfg
|
||
|
|
assign mod_sel_sideband = modmr ;
|
||
|
|
//DSP cfg
|
||
|
|
assign qam_nco_clr = mixncocr ;
|
||
|
|
assign qam_fcw = {mixnfcwhr,mixnfcwlr} ;
|
||
|
|
assign qam_pha = mixnphar ;
|
||
|
|
assign qam_mod = mixodtr ;
|
||
|
|
assign qam_sel_sideband = mixmr ;
|
||
|
|
assign intp_mode = intpmr ;
|
||
|
|
assign dac_mode_sel = mixodfr ;
|
||
|
|
assign qam_nco_sclr_en = mixncoscer ;
|
||
|
|
assign role_sel = roler ;
|
||
|
|
|
||
|
|
assign dout_sel = moddotr ;
|
||
|
|
|
||
|
|
assign dsp_alwayson = dspaor ;
|
||
|
|
//rddata
|
||
|
|
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n);
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
`undef MCUPARAR0
|
||
|
|
`undef MCUPARAR1
|
||
|
|
`undef MCUPARAR2
|
||
|
|
`undef MCUPARAR3
|
||
|
|
`undef MCURESR0
|
||
|
|
`undef MCURESR1
|
||
|
|
`undef MCURESR2
|
||
|
|
`undef MCURESR3
|
||
|
|
`undef RTIMR
|
||
|
|
`undef ICNTR
|
||
|
|
`undef FSIR
|
||
|
|
`undef MODMR
|
||
|
|
`undef INTPMR
|
||
|
|
`undef MIXNCOCR
|
||
|
|
`undef MIXNFCWHR
|
||
|
|
`undef MIXNFCWLR
|
||
|
|
`undef MIXNPHAR
|
||
|
|
`undef MIXMR
|
||
|
|
`undef MIXODTR
|
||
|
|
`undef MIXODFR
|
||
|
|
`undef MIXNCOSCER
|
||
|
|
`undef MODDOTR
|
||
|
|
`undef STR
|