SPI_Test/tb/testbench/Makefile

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Makefile
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2024-06-25 16:41:01 +08:00
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/100fs +nospecify -l compile.log
SIMV = ./simv -l sim.log
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -ssf *.fsdb -nologo &
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~