46 lines
734 B
Systemverilog
46 lines
734 B
Systemverilog
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class sysreg_monitor;
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virtual sysreg_if vif;
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virtual sram_if#(25,32) xif;
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//collect
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sysreg_trans act_trans[$];
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function new();
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endfunction
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extern task collect();
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extern task do_mon();
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endclass : sysreg_monitor
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task sysreg_monitor::do_mon();
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while(1) begin
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@(negedge xif.wren);
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collect();
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end
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endtask: do_mon
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task sysreg_monitor::collect();
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sysreg_trans tr_temp;
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@(posedge xif.clk);
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@(negedge xif.clk);
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tr_temp = new();
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tr_temp.dbg_enable = vif.dbg_enable ;
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tr_temp.dbg_data_sel = vif.dbg_data_sel ;
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tr_temp.dbg_ch_sel = vif.dbg_ch_sel ;
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tr_temp.irq = vif.irq ;
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act_trans.push_back(tr_temp);
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endtask: collect
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