19 lines
288 B
Systemverilog
19 lines
288 B
Systemverilog
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interface sysreg_if(input clk,input rstn);
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//output port
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logic dbg_enable ;
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logic dbg_data_sel;
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logic [1 :0] dbg_ch_sel ;//[3:0]
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logic [32 :0] status ;
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logic [ 4 :0] soft_rstn ;
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logic irq ;
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endinterface : sysreg_if
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