90 lines
1.7 KiB
Systemverilog
90 lines
1.7 KiB
Systemverilog
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//For ram_regfile
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class ram_refmodel;
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virtual spi_if wif;
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virtual sram_if#(25,32) xif;
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int base_addr;
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int sel;
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//poor-quality register model
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bit [31:0] rm1[8192];
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bit [31:0] rm2[ 64];
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bit [31:0] rm3[1024];
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//members to be sent to scoreboard
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int rst_error[5];
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bit[31:0] dout[$];
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spi_trans ramout[$];
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function new();
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endfunction
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extern task do_imitate();
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extern task RWreg_write (bit[24:0] addr,bit[32:0] din);
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extern task reg_read (bit[24:0] addr );
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endclass : ram_refmodel
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task ram_refmodel::do_imitate();
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int i=0,j=0;
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fork
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while(1) begin: write_reg_RW
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@(negedge xif.wren);
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RWreg_write(xif.addr,xif.din);
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end: write_reg_RW
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while(1) begin: read_reg
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@(negedge xif.rden);
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// repeat(3) @(posedge xif.clk);
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reg_read(xif.addr);
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end: read_reg
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join
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endtask: do_imitate
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task ram_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din);
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@(posedge wif.clk);
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if(addr[24:20] == base_addr) begin
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case(sel)
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1:rm1[addr[15:2]] = din;
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2:rm2[addr[15:2]] = din;
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3:rm3[addr[15:2]] = din;
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endcase
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end
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//$display("addr:%0h",addr);
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//$display("rm[%d]:%h",addr[15:2],rm2[addr[15:2]]);
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//$display("din:%h",din);
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endtask: RWreg_write
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task ram_refmodel::reg_read(bit[24:0] addr);
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@(posedge wif.clk);
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if(addr[24:20] == base_addr) begin
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case(sel)
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1:dout.push_back(rm1[ addr[14:2]]);
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2:dout.push_back(rm2[ addr[14:2]]);
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3:dout.push_back(rm3[ addr[14:2]]);
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endcase
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end
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// $display("dout:%h",dout[$]);
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endtask: reg_read
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