143 lines
2.8 KiB
ArmAsm
143 lines
2.8 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# breakpoint.S
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#-----------------------------------------------------------------------------
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#
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# Test breakpoints, if they are implemented.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV64M
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RVTEST_CODE_BEGIN
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# Set up breakpoint to trap on M-mode fetches.
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li TESTNUM, 2
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# Set tcontrol.mte, otherwise breakpoints are disabled. This may trap,
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# because tcontrol is an optional register.
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la a0, 1f
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csrrw a0, mtvec, a0
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li a1, 0x8
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csrs tcontrol, a1
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.p2align 2
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1:
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csrw mtvec, a0
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# Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
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csrsi mstatus, MSTATUS_MIE
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# Skip tselect if hard-wired.
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csrw tselect, x0
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csrr a1, tselect
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bne x0, a1, pass
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la a2, 1f
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csrw tdata2, a2
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li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE
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csrw tdata1, a0
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# Skip if breakpoint type is unsupported.
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csrr a1, tdata1
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bne a0, a1, 2f
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.align 2
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1:
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# Trap handler should skip this instruction.
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beqz x0, fail
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# Make sure reads don't trap.
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li TESTNUM, 3
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lw a0, (a2)
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2:
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# Set up breakpoint to trap on M-mode reads.
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li TESTNUM, 4
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li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD
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csrw tdata1, a0
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# Skip if breakpoint type is unsupported.
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csrr a1, tdata1
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bne a0, a1, 2f
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la a2, data1
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csrw tdata2, a2
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# Trap handler should skip this instruction.
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lw a2, (a2)
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beqz a2, fail
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# Make sure writes don't trap.
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li TESTNUM, 5
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sw x0, (a2)
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2:
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# Set up breakpoint to trap on M-mode stores.
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li TESTNUM, 6
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li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_STORE
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csrw tdata1, a0
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# Skip if breakpoint type is unsupported.
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csrr a1, tdata1
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bne a0, a1, 2f
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# Trap handler should skip this instruction.
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sw a2, (a2)
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# Make sure store didn't succeed.
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li TESTNUM, 7
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lw a2, (a2)
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bnez a2, fail
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# Try to set up a second breakpoint.
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li a0, 1
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csrw tselect, a0
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csrr a1, tselect
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bne a0, a1, pass
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li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD
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csrw tdata1, a0
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la a3, data2
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csrw tdata2, a3
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# Make sure the second breakpoint triggers.
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li TESTNUM, 8
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lw a3, (a3)
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beqz a3, fail
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# Make sure the first breakpoint still triggers.
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li TESTNUM, 10
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la a2, data1
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sw a2, (a2)
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li TESTNUM, 11
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lw a2, (a2)
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bnez a2, fail
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2:
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TEST_PASSFAIL
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.align 2
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.global mtvec_handler
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mtvec_handler:
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# Only even-numbered tests should trap.
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andi t0, TESTNUM, 1
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bnez t0, fail
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li t0, CAUSE_BREAKPOINT
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csrr t1, mcause
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bne t0, t1, fail
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csrr t0, mepc
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addi t0, t0, 4
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csrw mepc, t0
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mret
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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data1: .word 0
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data2: .word 0
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RVTEST_DATA_END
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