71 lines
1.1 KiB
ArmAsm
71 lines
1.1 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# access.S
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#-----------------------------------------------------------------------------
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#
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# Test access-exception behavior.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV64M
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RVTEST_CODE_BEGIN
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.align 2
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# Flipping just the MSB should result in an illegal address for RV64.
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la t2, fail
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li t0, 1 << (__riscv_xlen - 1)
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xor t0, t0, t2
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# jalr to an illegal address should commit (hence should write rd).
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# after the pc is set to rs1, an access exception should be raised.
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li TESTNUM, 2
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li t1, CAUSE_FETCH_ACCESS
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la s1, 1f
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li t2, 0
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jalr t2, t0
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1:
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# A load to an illegal address should not commit.
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li TESTNUM, 3
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li t1, CAUSE_LOAD_ACCESS
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la s1, 1f
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mv t2, s1
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lb t2, (t0)
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j fail
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1:
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j pass
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TEST_PASSFAIL
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.align 2
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.global mtvec_handler
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mtvec_handler:
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li a0, 2
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beq TESTNUM, a0, 2f
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li a0, 3
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beq TESTNUM, a0, 2f
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j fail
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2:
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bne t2, s1, fail
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csrr t2, mcause
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bne t2, t1, fail
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csrw mepc, s1
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mret
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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