SPI_Test/tb/qumcu/isa/case/Slt_test/main.s

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ArmAsm
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2024-06-25 16:41:01 +08:00
addi x1, x0,100
addi x2, x0,50
loop:
slt x4,x1,x2
addi x1, x1,-1
bne x1,x0,loop