27 lines
713 B
Systemverilog
27 lines
713 B
Systemverilog
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initial begin
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#10ns;
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wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[1].rfno0.rf_dfflr.qout_r == 32'h18);
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wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[6].rfno0.rf_dfflr.qout_r == 32'h01234000);
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wait(tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.regfile[7].rfno0.rf_dfflr.qout_r == 32'h08765008);
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wait(`TB_DRAM.mem[0] == 32'h01004000);
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wait(`TB_DRAM.mem[1] == 32'h08765008);
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TEST_PASS;
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end
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initial begin
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#100us;
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$display("\n");
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$display("*\tDDATA: 0x00: %h", `TB_DRAM.mem[0]);
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$display("*\tDDATA: 0x04: %h", `TB_DRAM.mem[1]);
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$display("\n----------------------------------------\n");
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$display("\t Timeout Error !!!!\n");
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TEST_FAIL;
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end
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