204 lines
6.9 KiB
Systemverilog
204 lines
6.9 KiB
Systemverilog
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wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
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wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
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wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
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wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
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reg ram_cs_dly1 ;
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reg reg_en_dly1 ;
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always @(posedge ram_clk) begin
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ram_cs_dly1 <= ~ram_cs;
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reg_en_dly1 <= reg_en;
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end
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initial begin
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#1ns;
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//@(posedge ram_cs_dly1 );
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#5ns;
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//while(1)begin
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#1ns;
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//@(posedge reg_en_dly1 );
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REGFILE_CHECK(6'd1 ,32'haaaa_a000);
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REGFILE_CHECK(6'd1 ,32'haaaa_a004);
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REGFILE_CHECK(6'd1 ,32'haaaa_a008);
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REGFILE_CHECK(6'd1 ,32'haaaa_a00c);
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REGFILE_CHECK(6'd2 ,32'haaaa_a010);
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REGFILE_CHECK(6'd2 ,32'haaaa_a014);
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REGFILE_CHECK(6'd2 ,32'haaaa_a018);
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REGFILE_CHECK(6'd2 ,32'haaaa_a01c);
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REGFILE_CHECK(6'd3 ,32'haaaa_a020);
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REGFILE_CHECK(6'd3 ,32'haaaa_a024);
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REGFILE_CHECK(6'd3 ,32'haaaa_a028);
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REGFILE_CHECK(6'd3 ,32'haaaa_a02c);
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REGFILE_CHECK(6'd4 ,32'haaaa_a030);
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REGFILE_CHECK(6'd4 ,32'haaaa_a034);
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REGFILE_CHECK(6'd4 ,32'haaaa_a038);
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REGFILE_CHECK(6'd4 ,32'haaaa_a03c);
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REGFILE_CHECK(6'd5 ,32'haaaa_a040);
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REGFILE_CHECK(6'd5 ,32'haaaa_a044);
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REGFILE_CHECK(6'd5 ,32'haaaa_a048);
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REGFILE_CHECK(6'd5 ,32'haaaa_a04c);
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REGFILE_CHECK(6'd6 ,32'haaaa_a050);
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REGFILE_CHECK(6'd6 ,32'haaaa_a054);
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REGFILE_CHECK(6'd6 ,32'haaaa_a058);
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REGFILE_CHECK(6'd6 ,32'haaaa_a05c);
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REGFILE_CHECK(6'd7 ,32'haaaa_a060);
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REGFILE_CHECK(6'd7 ,32'haaaa_a064);
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REGFILE_CHECK(6'd7 ,32'haaaa_a068);
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REGFILE_CHECK(6'd7 ,32'haaaa_a06c);
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REGFILE_CHECK(6'd8 ,32'haaaa_a070);
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REGFILE_CHECK(6'd8 ,32'haaaa_a074);
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REGFILE_CHECK(6'd8 ,32'haaaa_a078);
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REGFILE_CHECK(6'd8 ,32'haaaa_a07c);
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REGFILE_CHECK(6'd9 ,32'haaaa_a080);
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REGFILE_CHECK(6'd9 ,32'haaaa_a084);
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REGFILE_CHECK(6'd9 ,32'haaaa_a088);
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REGFILE_CHECK(6'd9 ,32'haaaa_a08c);
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REGFILE_CHECK(6'd10,32'haaaa_a090);
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REGFILE_CHECK(6'd10,32'haaaa_a094);
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REGFILE_CHECK(6'd10,32'haaaa_a098);
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REGFILE_CHECK(6'd10,32'haaaa_a09c);
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REGFILE_CHECK(6'd11,32'haaaa_a0a0);
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REGFILE_CHECK(6'd11,32'haaaa_a0a4);
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REGFILE_CHECK(6'd11,32'haaaa_a0a8);
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REGFILE_CHECK(6'd11,32'haaaa_a0ac);
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REGFILE_CHECK(6'd12,32'haaaa_a0b0);
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REGFILE_CHECK(6'd12,32'haaaa_a0b4);
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REGFILE_CHECK(6'd12,32'haaaa_a0b8);
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REGFILE_CHECK(6'd12,32'haaaa_a0bc);
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REGFILE_CHECK(6'd13,32'haaaa_a0c0);
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REGFILE_CHECK(6'd13,32'haaaa_a0c4);
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REGFILE_CHECK(6'd13,32'haaaa_a0c8);
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REGFILE_CHECK(6'd13,32'haaaa_a0cc);
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REGFILE_CHECK(6'd14,32'haaaa_a0d0);
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REGFILE_CHECK(6'd14,32'haaaa_a0d4);
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REGFILE_CHECK(6'd14,32'haaaa_a0d8);
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REGFILE_CHECK(6'd14,32'haaaa_a0dc);
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REGFILE_CHECK(6'd15,32'haaaa_a0e0);
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REGFILE_CHECK(6'd15,32'haaaa_a0e4);
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REGFILE_CHECK(6'd15,32'haaaa_a0e8);
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REGFILE_CHECK(6'd15,32'haaaa_a0ec);
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REGFILE_CHECK(6'd16,32'haaaa_a0f0);
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REGFILE_CHECK(6'd16,32'haaaa_a0f4);
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REGFILE_CHECK(6'd16,32'haaaa_a0f8);
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REGFILE_CHECK(6'd16,32'haaaa_a0fc);
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REGFILE_CHECK(6'd17,32'haaaa_a100);
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REGFILE_CHECK(6'd17,32'haaaa_a104);
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REGFILE_CHECK(6'd17,32'haaaa_a108);
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REGFILE_CHECK(6'd17,32'haaaa_a10c);
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REGFILE_CHECK(6'd18,32'haaaa_a110);
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REGFILE_CHECK(6'd18,32'haaaa_a114);
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REGFILE_CHECK(6'd18,32'haaaa_a118);
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REGFILE_CHECK(6'd18,32'haaaa_a11c);
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REGFILE_CHECK(6'd19,32'haaaa_a120);
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REGFILE_CHECK(6'd19,32'haaaa_a124);
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REGFILE_CHECK(6'd19,32'haaaa_a128);
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REGFILE_CHECK(6'd19,32'haaaa_a12c);
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REGFILE_CHECK(6'd20,32'haaaa_a130);
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REGFILE_CHECK(6'd20,32'haaaa_a134);
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REGFILE_CHECK(6'd20,32'haaaa_a138);
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REGFILE_CHECK(6'd20,32'haaaa_a13c);
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REGFILE_CHECK(6'd21,32'haaaa_a140);
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REGFILE_CHECK(6'd21,32'haaaa_a144);
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REGFILE_CHECK(6'd21,32'haaaa_a148);
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REGFILE_CHECK(6'd21,32'haaaa_a14c);
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REGFILE_CHECK(6'd22,32'haaaa_a150);
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REGFILE_CHECK(6'd22,32'haaaa_a154);
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REGFILE_CHECK(6'd22,32'haaaa_a158);
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REGFILE_CHECK(6'd22,32'haaaa_a15c);
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REGFILE_CHECK(6'd23,32'haaaa_a160);
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REGFILE_CHECK(6'd23,32'haaaa_a164);
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REGFILE_CHECK(6'd23,32'haaaa_a168);
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REGFILE_CHECK(6'd23,32'haaaa_a16c);
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REGFILE_CHECK(6'd24,32'haaaa_a170);
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REGFILE_CHECK(6'd24,32'haaaa_a174);
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REGFILE_CHECK(6'd24,32'haaaa_a178);
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REGFILE_CHECK(6'd24,32'haaaa_a17c);
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REGFILE_CHECK(6'd25,32'haaaa_a180);
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REGFILE_CHECK(6'd25,32'haaaa_a184);
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REGFILE_CHECK(6'd25,32'haaaa_a188);
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REGFILE_CHECK(6'd25,32'haaaa_a18c);
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REGFILE_CHECK(6'd26,32'haaaa_a190);
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REGFILE_CHECK(6'd26,32'haaaa_a194);
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REGFILE_CHECK(6'd26,32'haaaa_a198);
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REGFILE_CHECK(6'd26,32'haaaa_a19c);
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REGFILE_CHECK(6'd27,32'haaaa_a1a0);
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REGFILE_CHECK(6'd27,32'haaaa_a1a4);
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REGFILE_CHECK(6'd27,32'haaaa_a1a8);
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REGFILE_CHECK(6'd27,32'haaaa_a1ac);
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REGFILE_CHECK(6'd28,32'haaaa_a1b0);
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REGFILE_CHECK(6'd28,32'haaaa_a1b4);
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REGFILE_CHECK(6'd28,32'haaaa_a1b8);
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REGFILE_CHECK(6'd28,32'haaaa_a1bc);
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REGFILE_CHECK(6'd29,32'haaaa_a1c0);
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REGFILE_CHECK(6'd29,32'haaaa_a1c4);
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REGFILE_CHECK(6'd29,32'haaaa_a1c8);
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REGFILE_CHECK(6'd29,32'haaaa_a1cc);
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REGFILE_CHECK(6'd30,32'haaaa_a1d0);
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REGFILE_CHECK(6'd30,32'haaaa_a1d4);
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REGFILE_CHECK(6'd30,32'haaaa_a1d8);
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REGFILE_CHECK(6'd30,32'haaaa_a1dc);
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REGFILE_CHECK(6'd31,32'haaaa_a1e0);
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REGFILE_CHECK(6'd31,32'haaaa_a1e4);
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REGFILE_CHECK(6'd31,32'haaaa_a1e8);
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REGFILE_CHECK(6'd31,32'haaaa_a1ec);
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#10us;
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TEST_PASS;
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end
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task DRAM_DATA_CHECK;
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input [9:0] addr ;
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input [31:0] edata ;
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logic [31:0] ram_data;
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@(posedge ram_cs_dly1 );
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@(posedge ram_clk );
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//$monitor($time, " Simulation time: %t", $time);
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if(ram_cs_dly1) begin
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ram_data = `TB_DRAM.mem[addr];
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//$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
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if(ram_data !== edata) begin
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
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#1us;
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TEST_FAIL;
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end
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
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end
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else begin
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$display("* DRAM CS is High => Error!!!");
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TEST_FAIL;
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end
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endtask
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task REGFILE_CHECK;
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input [4:0] addr ;
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input [31:0] edata ;
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logic [31:0] reg_data;
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@(posedge reg_en );
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@(posedge reg_clk);
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if(reg_en)begin
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reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
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if(reg_data !== edata) begin
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
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#1us;
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//TEST_FAIL;
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end
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
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end
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else begin
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$display("* REG WR EN is High => Error!!!");
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//TEST_FAIL;
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end
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endtask
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initial begin
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#100us;
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$display("\n----------------------------------------\n");
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$display("\t Timeout Error !!!!\n");
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TEST_FAIL;
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end
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