204 lines
6.9 KiB
Systemverilog
204 lines
6.9 KiB
Systemverilog
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wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
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wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
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wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
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wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
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reg ram_cs_dly1 ;
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reg reg_en_dly1 ;
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always @(posedge ram_clk) begin
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ram_cs_dly1 <= ~ram_cs;
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reg_en_dly1 <= reg_en;
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end
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initial begin
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#1ns;
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//@(posedge ram_cs_dly1 );
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#5ns;
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//while(1)begin
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#1ns;
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//@(posedge reg_en_dly1 );
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REGFILE_CHECK(6'd1 ,32'h5555_5000);
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REGFILE_CHECK(6'd1 ,32'h5555_5004);
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REGFILE_CHECK(6'd1 ,32'h5555_5008);
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REGFILE_CHECK(6'd1 ,32'h5555_500c);
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REGFILE_CHECK(6'd2 ,32'h5555_5010);
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REGFILE_CHECK(6'd2 ,32'h5555_5014);
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REGFILE_CHECK(6'd2 ,32'h5555_5018);
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REGFILE_CHECK(6'd2 ,32'h5555_501c);
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REGFILE_CHECK(6'd3 ,32'h5555_5020);
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REGFILE_CHECK(6'd3 ,32'h5555_5024);
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REGFILE_CHECK(6'd3 ,32'h5555_5028);
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REGFILE_CHECK(6'd3 ,32'h5555_502c);
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REGFILE_CHECK(6'd4 ,32'h5555_5030);
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REGFILE_CHECK(6'd4 ,32'h5555_5034);
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REGFILE_CHECK(6'd4 ,32'h5555_5038);
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REGFILE_CHECK(6'd4 ,32'h5555_503c);
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REGFILE_CHECK(6'd5 ,32'h5555_5040);
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REGFILE_CHECK(6'd5 ,32'h5555_5044);
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REGFILE_CHECK(6'd5 ,32'h5555_5048);
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REGFILE_CHECK(6'd5 ,32'h5555_504c);
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REGFILE_CHECK(6'd6 ,32'h5555_5050);
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REGFILE_CHECK(6'd6 ,32'h5555_5054);
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REGFILE_CHECK(6'd6 ,32'h5555_5058);
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REGFILE_CHECK(6'd6 ,32'h5555_505c);
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REGFILE_CHECK(6'd7 ,32'h5555_5060);
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REGFILE_CHECK(6'd7 ,32'h5555_5064);
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REGFILE_CHECK(6'd7 ,32'h5555_5068);
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REGFILE_CHECK(6'd7 ,32'h5555_506c);
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REGFILE_CHECK(6'd8 ,32'h5555_5070);
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REGFILE_CHECK(6'd8 ,32'h5555_5074);
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REGFILE_CHECK(6'd8 ,32'h5555_5078);
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REGFILE_CHECK(6'd8 ,32'h5555_507c);
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REGFILE_CHECK(6'd9 ,32'h5555_5080);
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REGFILE_CHECK(6'd9 ,32'h5555_5084);
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REGFILE_CHECK(6'd9 ,32'h5555_5088);
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REGFILE_CHECK(6'd9 ,32'h5555_508c);
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REGFILE_CHECK(6'd10,32'h5555_5090);
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REGFILE_CHECK(6'd10,32'h5555_5094);
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REGFILE_CHECK(6'd10,32'h5555_5098);
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REGFILE_CHECK(6'd10,32'h5555_509c);
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REGFILE_CHECK(6'd11,32'h5555_50a0);
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REGFILE_CHECK(6'd11,32'h5555_50a4);
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REGFILE_CHECK(6'd11,32'h5555_50a8);
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REGFILE_CHECK(6'd11,32'h5555_50ac);
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REGFILE_CHECK(6'd12,32'h5555_50b0);
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REGFILE_CHECK(6'd12,32'h5555_50b4);
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REGFILE_CHECK(6'd12,32'h5555_50b8);
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REGFILE_CHECK(6'd12,32'h5555_50bc);
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REGFILE_CHECK(6'd13,32'h5555_50c0);
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REGFILE_CHECK(6'd13,32'h5555_50c4);
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REGFILE_CHECK(6'd13,32'h5555_50c8);
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REGFILE_CHECK(6'd13,32'h5555_50cc);
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REGFILE_CHECK(6'd14,32'h5555_50d0);
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REGFILE_CHECK(6'd14,32'h5555_50d4);
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REGFILE_CHECK(6'd14,32'h5555_50d8);
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REGFILE_CHECK(6'd14,32'h5555_50dc);
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REGFILE_CHECK(6'd15,32'h5555_50e0);
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REGFILE_CHECK(6'd15,32'h5555_50e4);
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REGFILE_CHECK(6'd15,32'h5555_50e8);
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REGFILE_CHECK(6'd15,32'h5555_50ec);
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REGFILE_CHECK(6'd16,32'h5555_50f0);
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REGFILE_CHECK(6'd16,32'h5555_50f4);
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REGFILE_CHECK(6'd16,32'h5555_50f8);
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REGFILE_CHECK(6'd16,32'h5555_50fc);
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REGFILE_CHECK(6'd17,32'h5555_5100);
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REGFILE_CHECK(6'd17,32'h5555_5104);
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REGFILE_CHECK(6'd17,32'h5555_5108);
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REGFILE_CHECK(6'd17,32'h5555_510c);
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REGFILE_CHECK(6'd18,32'h5555_5110);
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REGFILE_CHECK(6'd18,32'h5555_5114);
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REGFILE_CHECK(6'd18,32'h5555_5118);
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REGFILE_CHECK(6'd18,32'h5555_511c);
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REGFILE_CHECK(6'd19,32'h5555_5120);
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REGFILE_CHECK(6'd19,32'h5555_5124);
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REGFILE_CHECK(6'd19,32'h5555_5128);
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REGFILE_CHECK(6'd19,32'h5555_512c);
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REGFILE_CHECK(6'd20,32'h5555_5130);
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REGFILE_CHECK(6'd20,32'h5555_5134);
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REGFILE_CHECK(6'd20,32'h5555_5138);
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REGFILE_CHECK(6'd20,32'h5555_513c);
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REGFILE_CHECK(6'd21,32'h5555_5140);
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REGFILE_CHECK(6'd21,32'h5555_5144);
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REGFILE_CHECK(6'd21,32'h5555_5148);
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REGFILE_CHECK(6'd21,32'h5555_514c);
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REGFILE_CHECK(6'd22,32'h5555_5150);
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REGFILE_CHECK(6'd22,32'h5555_5154);
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REGFILE_CHECK(6'd22,32'h5555_5158);
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REGFILE_CHECK(6'd22,32'h5555_515c);
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REGFILE_CHECK(6'd23,32'h5555_5160);
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REGFILE_CHECK(6'd23,32'h5555_5164);
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REGFILE_CHECK(6'd23,32'h5555_5168);
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REGFILE_CHECK(6'd23,32'h5555_516c);
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REGFILE_CHECK(6'd24,32'h5555_5170);
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REGFILE_CHECK(6'd24,32'h5555_5174);
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REGFILE_CHECK(6'd24,32'h5555_5178);
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REGFILE_CHECK(6'd24,32'h5555_517c);
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REGFILE_CHECK(6'd25,32'h5555_5180);
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REGFILE_CHECK(6'd25,32'h5555_5184);
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REGFILE_CHECK(6'd25,32'h5555_5188);
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REGFILE_CHECK(6'd25,32'h5555_518c);
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REGFILE_CHECK(6'd26,32'h5555_5190);
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REGFILE_CHECK(6'd26,32'h5555_5194);
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REGFILE_CHECK(6'd26,32'h5555_5198);
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REGFILE_CHECK(6'd26,32'h5555_519c);
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REGFILE_CHECK(6'd27,32'h5555_51a0);
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REGFILE_CHECK(6'd27,32'h5555_51a4);
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REGFILE_CHECK(6'd27,32'h5555_51a8);
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REGFILE_CHECK(6'd27,32'h5555_51ac);
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REGFILE_CHECK(6'd28,32'h5555_51b0);
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REGFILE_CHECK(6'd28,32'h5555_51b4);
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REGFILE_CHECK(6'd28,32'h5555_51b8);
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REGFILE_CHECK(6'd28,32'h5555_51bc);
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REGFILE_CHECK(6'd29,32'h5555_51c0);
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REGFILE_CHECK(6'd29,32'h5555_51c4);
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REGFILE_CHECK(6'd29,32'h5555_51c8);
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REGFILE_CHECK(6'd29,32'h5555_51cc);
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REGFILE_CHECK(6'd30,32'h5555_51d0);
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REGFILE_CHECK(6'd30,32'h5555_51d4);
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REGFILE_CHECK(6'd30,32'h5555_51d8);
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REGFILE_CHECK(6'd30,32'h5555_51dc);
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REGFILE_CHECK(6'd31,32'h5555_51e0);
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REGFILE_CHECK(6'd31,32'h5555_51e4);
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REGFILE_CHECK(6'd31,32'h5555_51e8);
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REGFILE_CHECK(6'd31,32'h5555_51ec);
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#10us;
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TEST_PASS;
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end
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task DRAM_DATA_CHECK;
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input [9:0] addr ;
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input [31:0] edata ;
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logic [31:0] ram_data;
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@(posedge ram_cs_dly1 );
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@(posedge ram_clk );
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//$monitor($time, " Simulation time: %t", $time);
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if(ram_cs_dly1) begin
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ram_data = `TB_DRAM.mem[addr];
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//$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
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if(ram_data !== edata) begin
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
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#1us;
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TEST_FAIL;
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end
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
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end
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else begin
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$display("* DRAM CS is High => Error!!!");
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TEST_FAIL;
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end
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endtask
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task REGFILE_CHECK;
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input [4:0] addr ;
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input [31:0] edata ;
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logic [31:0] reg_data;
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@(posedge reg_en );
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@(posedge reg_clk);
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if(reg_en)begin
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reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
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if(reg_data !== edata) begin
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
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#1us;
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//TEST_FAIL;
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end
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
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end
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else begin
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$display("* REG WR EN is High => Error!!!");
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//TEST_FAIL;
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end
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endtask
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initial begin
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#100us;
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$display("\n----------------------------------------\n");
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$display("\t Timeout Error !!!!\n");
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TEST_FAIL;
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end
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