204 lines
6.9 KiB
Systemverilog
204 lines
6.9 KiB
Systemverilog
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wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
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wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
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wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
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wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
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reg ram_cs_dly1 ;
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reg reg_en_dly1 ;
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always @(posedge ram_clk) begin
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ram_cs_dly1 <= ~ram_cs;
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reg_en_dly1 <= reg_en;
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end
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initial begin
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#1ns;
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//@(posedge ram_cs_dly1 );
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#5ns;
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//while(1)begin
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#1ns;
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//@(posedge reg_en_dly1 );
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REGFILE_CHECK(6'd1 ,32'h0000_0000);
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REGFILE_CHECK(6'd1 ,32'h0000_0004);
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REGFILE_CHECK(6'd1 ,32'h0000_0008);
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REGFILE_CHECK(6'd1 ,32'h0000_000c);
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REGFILE_CHECK(6'd2 ,32'h0000_0010);
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REGFILE_CHECK(6'd2 ,32'h0000_0014);
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REGFILE_CHECK(6'd2 ,32'h0000_0018);
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REGFILE_CHECK(6'd2 ,32'h0000_001c);
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REGFILE_CHECK(6'd3 ,32'h0000_0020);
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REGFILE_CHECK(6'd3 ,32'h0000_0024);
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REGFILE_CHECK(6'd3 ,32'h0000_0028);
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REGFILE_CHECK(6'd3 ,32'h0000_002c);
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REGFILE_CHECK(6'd4 ,32'h0000_0030);
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REGFILE_CHECK(6'd4 ,32'h0000_0034);
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REGFILE_CHECK(6'd4 ,32'h0000_0038);
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REGFILE_CHECK(6'd4 ,32'h0000_003c);
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REGFILE_CHECK(6'd5 ,32'h0000_0040);
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REGFILE_CHECK(6'd5 ,32'h0000_0044);
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REGFILE_CHECK(6'd5 ,32'h0000_0048);
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REGFILE_CHECK(6'd5 ,32'h0000_004c);
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REGFILE_CHECK(6'd6 ,32'h0000_0050);
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REGFILE_CHECK(6'd6 ,32'h0000_0054);
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REGFILE_CHECK(6'd6 ,32'h0000_0058);
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REGFILE_CHECK(6'd6 ,32'h0000_005c);
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REGFILE_CHECK(6'd7 ,32'h0000_0060);
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REGFILE_CHECK(6'd7 ,32'h0000_0064);
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REGFILE_CHECK(6'd7 ,32'h0000_0068);
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REGFILE_CHECK(6'd7 ,32'h0000_006c);
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REGFILE_CHECK(6'd8 ,32'h0000_0070);
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REGFILE_CHECK(6'd8 ,32'h0000_0074);
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REGFILE_CHECK(6'd8 ,32'h0000_0078);
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REGFILE_CHECK(6'd8 ,32'h0000_007c);
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REGFILE_CHECK(6'd9 ,32'h0000_0080);
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REGFILE_CHECK(6'd9 ,32'h0000_0084);
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REGFILE_CHECK(6'd9 ,32'h0000_0088);
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REGFILE_CHECK(6'd9 ,32'h0000_008c);
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REGFILE_CHECK(6'd10,32'h0000_0090);
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REGFILE_CHECK(6'd10,32'h0000_0094);
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REGFILE_CHECK(6'd10,32'h0000_0098);
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REGFILE_CHECK(6'd10,32'h0000_009c);
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REGFILE_CHECK(6'd11,32'h0000_00a0);
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REGFILE_CHECK(6'd11,32'h0000_00a4);
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REGFILE_CHECK(6'd11,32'h0000_00a8);
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REGFILE_CHECK(6'd11,32'h0000_00ac);
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REGFILE_CHECK(6'd12,32'h0000_00b0);
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REGFILE_CHECK(6'd12,32'h0000_00b4);
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REGFILE_CHECK(6'd12,32'h0000_00b8);
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REGFILE_CHECK(6'd12,32'h0000_00bc);
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REGFILE_CHECK(6'd13,32'h0000_00c0);
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REGFILE_CHECK(6'd13,32'h0000_00c4);
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REGFILE_CHECK(6'd13,32'h0000_00c8);
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REGFILE_CHECK(6'd13,32'h0000_00cc);
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REGFILE_CHECK(6'd14,32'h0000_00d0);
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REGFILE_CHECK(6'd14,32'h0000_00d4);
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REGFILE_CHECK(6'd14,32'h0000_00d8);
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REGFILE_CHECK(6'd14,32'h0000_00dc);
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REGFILE_CHECK(6'd15,32'h0000_00e0);
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REGFILE_CHECK(6'd15,32'h0000_00e4);
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REGFILE_CHECK(6'd15,32'h0000_00e8);
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REGFILE_CHECK(6'd15,32'h0000_00ec);
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REGFILE_CHECK(6'd16,32'h0000_00f0);
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REGFILE_CHECK(6'd16,32'h0000_00f4);
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REGFILE_CHECK(6'd16,32'h0000_00f8);
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REGFILE_CHECK(6'd16,32'h0000_00fc);
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REGFILE_CHECK(6'd17,32'h0000_0100);
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REGFILE_CHECK(6'd17,32'h0000_0104);
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REGFILE_CHECK(6'd17,32'h0000_0108);
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REGFILE_CHECK(6'd17,32'h0000_010c);
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REGFILE_CHECK(6'd18,32'h0000_0110);
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REGFILE_CHECK(6'd18,32'h0000_0114);
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REGFILE_CHECK(6'd18,32'h0000_0118);
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REGFILE_CHECK(6'd18,32'h0000_011c);
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REGFILE_CHECK(6'd19,32'h0000_0120);
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REGFILE_CHECK(6'd19,32'h0000_0124);
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REGFILE_CHECK(6'd19,32'h0000_0128);
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REGFILE_CHECK(6'd19,32'h0000_012c);
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REGFILE_CHECK(6'd20,32'h0000_0130);
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REGFILE_CHECK(6'd20,32'h0000_0134);
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REGFILE_CHECK(6'd20,32'h0000_0138);
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REGFILE_CHECK(6'd20,32'h0000_013c);
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REGFILE_CHECK(6'd21,32'h0000_0140);
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REGFILE_CHECK(6'd21,32'h0000_0144);
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REGFILE_CHECK(6'd21,32'h0000_0148);
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REGFILE_CHECK(6'd21,32'h0000_014c);
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REGFILE_CHECK(6'd22,32'h0000_0150);
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REGFILE_CHECK(6'd22,32'h0000_0154);
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REGFILE_CHECK(6'd22,32'h0000_0158);
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REGFILE_CHECK(6'd22,32'h0000_015c);
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REGFILE_CHECK(6'd23,32'h0000_0160);
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REGFILE_CHECK(6'd23,32'h0000_0164);
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REGFILE_CHECK(6'd23,32'h0000_0168);
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REGFILE_CHECK(6'd23,32'h0000_016c);
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REGFILE_CHECK(6'd24,32'h0000_0170);
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REGFILE_CHECK(6'd24,32'h0000_0174);
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REGFILE_CHECK(6'd24,32'h0000_0178);
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REGFILE_CHECK(6'd24,32'h0000_017c);
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REGFILE_CHECK(6'd25,32'h0000_0180);
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REGFILE_CHECK(6'd25,32'h0000_0184);
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REGFILE_CHECK(6'd25,32'h0000_0188);
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REGFILE_CHECK(6'd25,32'h0000_018c);
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REGFILE_CHECK(6'd26,32'h0000_0190);
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REGFILE_CHECK(6'd26,32'h0000_0194);
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REGFILE_CHECK(6'd26,32'h0000_0198);
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REGFILE_CHECK(6'd26,32'h0000_019c);
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REGFILE_CHECK(6'd27,32'h0000_01a0);
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REGFILE_CHECK(6'd27,32'h0000_01a4);
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REGFILE_CHECK(6'd27,32'h0000_01a8);
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REGFILE_CHECK(6'd27,32'h0000_01ac);
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REGFILE_CHECK(6'd28,32'h0000_01b0);
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REGFILE_CHECK(6'd28,32'h0000_01b4);
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REGFILE_CHECK(6'd28,32'h0000_01b8);
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REGFILE_CHECK(6'd28,32'h0000_01bc);
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REGFILE_CHECK(6'd29,32'h0000_01c0);
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REGFILE_CHECK(6'd29,32'h0000_01c4);
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REGFILE_CHECK(6'd29,32'h0000_01c8);
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REGFILE_CHECK(6'd29,32'h0000_01cc);
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REGFILE_CHECK(6'd30,32'h0000_01d0);
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REGFILE_CHECK(6'd30,32'h0000_01d4);
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REGFILE_CHECK(6'd30,32'h0000_01d8);
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REGFILE_CHECK(6'd30,32'h0000_01dc);
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REGFILE_CHECK(6'd31,32'h0000_01e0);
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REGFILE_CHECK(6'd31,32'h0000_01e4);
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REGFILE_CHECK(6'd31,32'h0000_01e8);
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REGFILE_CHECK(6'd31,32'h0000_01ec);
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#10us;
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TEST_PASS;
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end
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task DRAM_DATA_CHECK;
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input [9:0] addr ;
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input [31:0] edata ;
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logic [31:0] ram_data;
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@(posedge ram_cs_dly1 );
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@(posedge ram_clk );
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//$monitor($time, " Simulation time: %t", $time);
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if(ram_cs_dly1) begin
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ram_data = `TB_DRAM.mem[addr];
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//$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
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if(ram_data !== edata) begin
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
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#1us;
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TEST_FAIL;
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end
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
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end
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else begin
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$display("* DRAM CS is High => Error!!!");
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TEST_FAIL;
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end
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endtask
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task REGFILE_CHECK;
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input [4:0] addr ;
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input [31:0] edata ;
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logic [31:0] reg_data;
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@(posedge reg_en );
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@(posedge reg_clk);
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if(reg_en)begin
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reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
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if(reg_data !== edata) begin
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
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#1us;
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//TEST_FAIL;
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end
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
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end
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else begin
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$display("* REG WR EN is High => Error!!!");
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//TEST_FAIL;
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end
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endtask
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initial begin
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#100us;
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$display("\n----------------------------------------\n");
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$display("\t Timeout Error !!!!\n");
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TEST_FAIL;
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end
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