176 lines
9.8 KiB
Systemverilog
176 lines
9.8 KiB
Systemverilog
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class pllreg_trans;
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rand bit pll_lock
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;rand bit pll_lock_time
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//output port
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;rand bit ref_sel // Clock source selection for a frequency divider;
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// 1'b1:External clock source
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// 1'b1:internal phase-locked loop clock source
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;rand bit ref_en // rand bit reference clock enable
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// 1'b1:enable;1'b1:disable
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;rand bit ref_s2d_en // Referenced clock differential to single-ended conversion enable
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// 1'b1:enable;1'b1:disable
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;rand bit [6 :0] p_cnt // P counter
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;rand bit pfd_delay // PFD Dead Zone
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;rand bit pfd_dff_Set // Setting the PFD register;active high
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;rand bit pfd_dff_4and // PFD rand bit polarity
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;rand bit [3 :0] spd_div // SPD Frequency Divider
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;rand bit spd_pulse_width // Pulse Width of SPD
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;rand bit spd_pulse_sw // Pulse sw of SPD
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;rand bit cpc_sel // current source selection
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;rand bit [1 :0] swcp_i // PTAT current switch
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;rand bit [3 :0] sw_ptat_r // PTAT current adjustment
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;rand bit [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
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;rand bit sw_fll_delay // PLL Dead Zone
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;rand bit pfd_sel // PFD Loop selection
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;rand bit spd_sel // SPD Loop selection
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;rand bit fll_sel // FLL Loop selection
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;rand bit vco_tc // VCO temperature compensation
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;rand bit vco_tcr // VCO temperature compensation resistor
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;rand bit vco_gain_adj // VCO gain adjustment
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;rand bit vco_gain_adj_r // VCO gain adjustment resistor
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;rand bit [2 :0] vco_cur_adj // VCO current adjustment
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;rand bit vco_buff_en // VCO buff enable;active high
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;rand bit vco_en // VCO enable;active high
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;rand bit [2 :0] pll_dpwr_adj // PLL frequency division rand bit power adjustment
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;rand bit [6 :0] vco_fb_adj // VCO frequency band adjustment
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;rand bit afc_en // AFC enable
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;rand bit afc_shutdown // AFC module shutdown signal
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;rand bit [0 :0] afc_det_speed // AFC detection speed
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;rand bit [0 :0] flag_out_sel // Read and choose the signs
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;rand bit afc_reset // AFC reset
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;rand bit [10 :0] afc_cnt // AFC frequency band adjustment function counter
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// counting time adjustment
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;rand bit [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection
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// feature counter
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;rand bit [3 :0] afc_pres // Adjusting the resolution of the AFC comparator
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;rand bit [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count
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;rand bit [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band
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// adjustment function
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;rand bit [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
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;rand bit [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
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;rand bit [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable
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;rand bit [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
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;rand bit [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable
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;rand bit sync_oe // SYNC signal output enable, hign active
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;rand bit clkrx_pdn; // Clock Rx Power down, Ative Low
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constraint cstr {
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pll_lock_time >= 0 ;
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pll_lock_time <= 3000 ;
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}
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function new();
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endfunction
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function bit[42:0] compare(pllreg_trans tr);
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bit[42:0] result=43'b0;
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if(tr.ref_sel != ref_sel ) result[ 0]=1'b1;
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if(tr.ref_en != ref_en ) result[ 1]=1'b1;
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if(tr.ref_s2d_en != ref_s2d_en ) result[ 2]=1'b1;
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if(tr.p_cnt != p_cnt ) result[ 3]=1'b1;
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if(tr.pfd_delay != pfd_delay ) result[ 4]=1'b1;
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if(tr.pfd_dff_Set != pfd_dff_Set ) result[ 5]=1'b1;
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if(tr.pfd_dff_4and != pfd_dff_4and ) result[ 6]=1'b1;
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if(tr.spd_div != spd_div ) result[ 7]=1'b1;
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if(tr.spd_pulse_width != spd_pulse_width ) result[ 8]=1'b1;
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if(tr.spd_pulse_sw != spd_pulse_sw ) result[ 9]=1'b1;
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if(tr.cpc_sel != cpc_sel ) result[10]=1'b1;
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if(tr.swcp_i != swcp_i ) result[11]=1'b1;
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if(tr.sw_ptat_r != sw_ptat_r ) result[12]=1'b1;
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if(tr.sw_fll_cpi != sw_fll_cpi ) result[13]=1'b1;
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if(tr.sw_fll_delay != sw_fll_delay ) result[14]=1'b1;
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if(tr.pfd_sel != pfd_sel ) result[15]=1'b1;
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if(tr.spd_sel != spd_sel ) result[16]=1'b1;
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if(tr.fll_sel != fll_sel ) result[17]=1'b1;
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if(tr.vco_tc != vco_tc ) result[18]=1'b1;
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if(tr.vco_tcr != vco_tcr ) result[19]=1'b1;
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if(tr.vco_gain_adj != vco_gain_adj ) result[20]=1'b1;
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if(tr.vco_gain_adj_r != vco_gain_adj_r ) result[21]=1'b1;
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if(tr.vco_cur_adj != vco_cur_adj ) result[22]=1'b1;
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if(tr.vco_buff_en != vco_buff_en ) result[23]=1'b1;
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if(tr.vco_en != vco_en ) result[24]=1'b1;
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if(tr.pll_dpwr_adj != pll_dpwr_adj ) result[25]=1'b1;
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if(tr.vco_fb_adj != vco_fb_adj ) result[26]=1'b1;
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if(tr.afc_en != afc_en ) result[27]=1'b1;
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if(tr.afc_shutdown != afc_shutdown ) result[28]=1'b1;
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if(tr.afc_det_speed != afc_det_speed ) result[29]=1'b1;
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if(tr.flag_out_sel != flag_out_sel ) result[30]=1'b1;
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if(tr.afc_reset != afc_reset ) result[31]=1'b1;
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if(tr.afc_cnt != afc_cnt ) result[32]=1'b1;
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if(tr.afc_ld_cnt != afc_ld_cnt ) result[33]=1'b1;
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if(tr.afc_pres != afc_pres ) result[34]=1'b1;
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if(tr.afc_ld_tcc != afc_ld_tcc ) result[35]=1'b1;
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if(tr.afc_fb_tcc != afc_fb_tcc ) result[36]=1'b1;
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if(tr.div_rstn_sel != div_rstn_sel ) result[37]=1'b1;
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if(tr.test_clk_sel != test_clk_sel ) result[38]=1'b1;
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if(tr.test_clk_oen != test_clk_oen ) result[39]=1'b1;
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if(tr.dig_clk_sel != dig_clk_sel ) result[40]=1'b1;
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if(tr.div_sync_en != div_sync_en ) result[41]=1'b1;
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if(tr.sync_oe != sync_oe ) result[42]=1'b1;
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return result;
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endfunction
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function print(bit[42:0] ctrl,integer fid);
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if(ctrl[ 0]) $fwrite(fid," ref_sel =%b\n", ref_sel );
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if(ctrl[ 1]) $fwrite(fid," ref_en =%b\n", ref_en );
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if(ctrl[ 2]) $fwrite(fid," ref_s2d_en =%b\n", ref_s2d_en );
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if(ctrl[ 3]) $fwrite(fid," p_cnt =%b\n", p_cnt );
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if(ctrl[ 4]) $fwrite(fid," pfd_delay =%b\n", pfd_delay );
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if(ctrl[ 5]) $fwrite(fid," pfd_dff_Set =%b\n", pfd_dff_Set );
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if(ctrl[ 6]) $fwrite(fid," pfd_dff_4and =%b\n", pfd_dff_4and );
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if(ctrl[ 7]) $fwrite(fid," spd_div =%b\n", spd_div );
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if(ctrl[ 8]) $fwrite(fid," spd_pulse_width =%b\n", spd_pulse_width);
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if(ctrl[ 9]) $fwrite(fid," spd_pulse_sw =%b\n", spd_pulse_sw );
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if(ctrl[10]) $fwrite(fid," cpc_sel =%b\n", cpc_sel );
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if(ctrl[11]) $fwrite(fid," swcp_i =%b\n", swcp_i );
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if(ctrl[12]) $fwrite(fid," sw_ptat_r =%b\n", sw_ptat_r );
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if(ctrl[13]) $fwrite(fid," sw_fll_cpi =%b\n", sw_fll_cpi );
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if(ctrl[14]) $fwrite(fid," sw_fll_delay =%b\n", sw_fll_delay );
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if(ctrl[15]) $fwrite(fid," pfd_sel =%b\n", pfd_sel );
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if(ctrl[16]) $fwrite(fid," spd_sel =%b\n", spd_sel );
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if(ctrl[17]) $fwrite(fid," fll_sel =%b\n", fll_sel );
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if(ctrl[18]) $fwrite(fid," vco_tc =%b\n", vco_tc );
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if(ctrl[19]) $fwrite(fid," vco_tcr =%b\n", vco_tcr );
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if(ctrl[20]) $fwrite(fid," vco_gain_adj =%b\n", vco_gain_adj );
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if(ctrl[21]) $fwrite(fid," vco_gain_adj_r =%b\n", vco_gain_adj_r );
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if(ctrl[22]) $fwrite(fid," vco_cur_adj =%b\n", vco_cur_adj );
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if(ctrl[23]) $fwrite(fid," vco_buff_en =%b\n", vco_buff_en );
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if(ctrl[24]) $fwrite(fid," vco_en =%b\n", vco_en );
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if(ctrl[25]) $fwrite(fid," pll_dpwr_adj =%b\n", pll_dpwr_adj );
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if(ctrl[26]) $fwrite(fid," vco_fb_adj =%b\n", vco_fb_adj );
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if(ctrl[27]) $fwrite(fid," afc_en =%b\n", afc_en );
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if(ctrl[28]) $fwrite(fid," afc_shutdown =%b\n", afc_shutdown );
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if(ctrl[29]) $fwrite(fid," afc_det_speed =%b\n", afc_det_speed );
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if(ctrl[30]) $fwrite(fid," flag_out_sel =%b\n", flag_out_sel );
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if(ctrl[31]) $fwrite(fid," afc_reset =%b\n", afc_reset );
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if(ctrl[32]) $fwrite(fid," afc_cnt =%b\n", afc_cnt );
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if(ctrl[33]) $fwrite(fid," afc_ld_cnt =%b\n", afc_ld_cnt );
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if(ctrl[34]) $fwrite(fid," afc_pres =%b\n", afc_pres );
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if(ctrl[35]) $fwrite(fid," afc_ld_tcc =%b\n", afc_ld_tcc );
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if(ctrl[36]) $fwrite(fid," afc_fb_tcc =%b\n", afc_fb_tcc );
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if(ctrl[37]) $fwrite(fid," div_rstn_sel =%b\n", div_rstn_sel );
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if(ctrl[38]) $fwrite(fid," test_clk_sel =%b\n", test_clk_sel );
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if(ctrl[39]) $fwrite(fid," test_clk_oen =%b\n", test_clk_oen );
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if(ctrl[40]) $fwrite(fid," dig_clk_sel =%b\n", dig_clk_sel );
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if(ctrl[41]) $fwrite(fid," div_sync_en =%b\n", div_sync_en );
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if(ctrl[42]) $fwrite(fid," sync_oe =%b\n", sync_oe );
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endfunction
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endclass : pllreg_trans
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