29 lines
898 B
Systemverilog
29 lines
898 B
Systemverilog
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interface mcureg_if(input clk,input rstn);
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//input port
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logic [3 :0] wrmask ;
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logic [2 :0] fb_st_info ;
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logic [31 :0] run_time ;
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logic [31 :0] instr_num ;
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logic [31 :0] mcu_param [3:0] ; // MCU parameter 0~3
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//output port
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logic [31 :0] mcu_result [3:0] ; // MCU result 0~3
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logic [31 :0] mcu_cwfr [3:0] ; // Carrier frequency ctrl word 0~3
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logic [31 :0] mcu_gapr [7:0] ; // Carrier phase ctrl word 0~3
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logic [31 :0] mcu_ampr [3:0] ; // Carrier Amplitude 0~3
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logic [31 :0] mcu_baisr [3:0] ; // Carrier Bais 0~3
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logic [1 :0] mcu_intp_sel ; //2'b00:HBF;2'b01:Nearest-neighbor interpolator;
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logic mcu_nco_pha_clr ;
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logic [15 :0] mcu_rz_pha ;
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endinterface : mcureg_if
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