125 lines
5.0 KiB
Systemverilog
125 lines
5.0 KiB
Systemverilog
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class awgreg_trans;
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rand bit[1 :0] fb_st_i ;
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rand bit[31 :0] run_time ;
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rand bit[31 :0] instr_num ;
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rand bit bais_i_ov ;
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rand bit bais_q_ov ;
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rand bit awg_ctrl_fsm_st ;
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rand bit[31 :0] mcu_result0 ; // MCU result 0
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rand bit[31 :0] mcu_result1 ; // MCU result 1
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rand bit[31 :0] mcu_result2 ; // MCU result 2
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rand bit[31 :0] mcu_result3 ; // MCU result 3
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rand bit[31 :0] fb_st_i_time ;
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rand bit[31 :0] run_time_time ;
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rand bit[31 :0] instr_num_time ;
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rand bit bais_i_ov_time ;
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rand bit bais_q_ov_time ;
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rand bit awg_ctrl_fsm_st_time ;
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rand bit[31 :0] mcu_result0_time ; // MCU result 0
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rand bit[31 :0] mcu_result1_time ; // MCU result 1
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rand bit[31 :0] mcu_result2_time ; // MCU result 2
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rand bit[31 :0] mcu_result3_time ; // MCU result 3
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//output port
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rand bit[31 :0] mcu_param0 ; // MCU parameter 0
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rand bit[31 :0] mcu_param1 ; // MCU parameter 1
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rand bit[31 :0] mcu_param2 ; // MCU parameter 2
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rand bit[31 :0] mcu_param3 ; // MCU parameter 3
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rand bit[2 :0] fb_st_o ;
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rand bit mod_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband;
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rand bit qam_nco_clr ;
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rand bit qam_nco_sclr_en ;
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rand bit[47 :0] qam_fcw ;
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rand bit[15 :0] qam_pha ;
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rand bit[1 :0] qam_mod ; //2'b00:bypass;2'b01:mix;2'b10:cos;2'b11:sin;
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rand bit qam_sel_sideband ; //1'b0:Upper sideband;1'b1:Lower sideband;
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rand bit[2 :0] intp_mode ; //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16;
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rand bit[1 :0] role_sel ; //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve;
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rand bit[1 :0] dac_mode_sel ; //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve;
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rand bit dout_sel ;
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constraint cstr {
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fb_st_i_time >= 0 ;
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run_time_time >= 0 ;
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instr_num_time >= 0 ;
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bais_i_ov_time >= 0 ;
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bais_q_ov_time >= 0 ;
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awg_ctrl_fsm_st_time >= 0 ;
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mcu_result0_time >= 0 ;
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mcu_result1_time >= 0 ;
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mcu_result2_time >= 0 ;
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mcu_result3_time >= 0 ;
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fb_st_i_time <= 2000 ;
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run_time_time <= 2000 ;
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instr_num_time <= 2000 ;
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bais_i_ov_time <= 2000 ;
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bais_q_ov_time <= 2000 ;
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awg_ctrl_fsm_st_time <= 2000 ;
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mcu_result0_time <= 2000 ;
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mcu_result1_time <= 2000 ;
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mcu_result2_time <= 2000 ;
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mcu_result3_time <= 2000 ;
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}
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function new();
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endfunction
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function bit[38:0] compare(awgreg_trans tr);
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bit[38:0] result=39'b0;
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if(tr.mcu_param0 != mcu_param0 ) result[ 0]=1'b1;
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if(tr.mcu_param1 != mcu_param1 ) result[ 1]=1'b1;
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if(tr.mcu_param2 != mcu_param2 ) result[ 2]=1'b1;
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if(tr.mcu_param3 != mcu_param3 ) result[ 3]=1'b1;
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if(tr.fb_st_o != fb_st_o ) result[ 4]=1'b1;
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if(tr.mod_sel_sideband != mod_sel_sideband ) result[ 5]=1'b1;
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if(tr.qam_nco_clr != qam_nco_clr ) result[ 6]=1'b1;
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if(tr.qam_nco_sclr_en != qam_nco_sclr_en ) result[ 7]=1'b1;
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if(tr.qam_fcw != qam_fcw ) result[ 8]=1'b1;
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if(tr.qam_pha != qam_pha ) result[ 9]=1'b1;
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if(tr.qam_mod != qam_mod ) result[10]=1'b1;
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if(tr.qam_sel_sideband != qam_sel_sideband ) result[11]=1'b1;
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if(tr.intp_mode != intp_mode ) result[12]=1'b1;
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if(tr.role_sel != role_sel ) result[13]=1'b1;
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if(tr.dac_mode_sel != dac_mode_sel ) result[14]=1'b1;
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if(tr.dout_sel != dout_sel ) result[15]=1'b1;
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return result;
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endfunction
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function print(bit[38:0] ctrl,integer fid);
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if(ctrl[ 0]) $fwrite(fid,"mcu_param0 =%h\n",mcu_param0 );
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if(ctrl[ 1]) $fwrite(fid,"mcu_param1 =%h\n",mcu_param1 );
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if(ctrl[ 2]) $fwrite(fid,"mcu_param2 =%h\n",mcu_param2 );
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if(ctrl[ 3]) $fwrite(fid,"mcu_param3 =%h\n",mcu_param3 );
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if(ctrl[ 4]) $fwrite(fid,"fb_st_o =%h\n",fb_st_o );
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if(ctrl[ 5]) $fwrite(fid,"mod_sel_sideband =%h\n",mod_sel_sideband );
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if(ctrl[ 6]) $fwrite(fid,"qam_nco_clr =%h\n",qam_nco_clr );
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if(ctrl[ 7]) $fwrite(fid,"qam_nco_sclr_en =%h\n",qam_nco_sclr_en );
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if(ctrl[ 8]) $fwrite(fid,"qam_fcw =%h\n",qam_fcw );
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if(ctrl[ 9]) $fwrite(fid,"qam_pha =%h\n",qam_pha );
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if(ctrl[10]) $fwrite(fid,"qam_mod =%h\n",qam_mod );
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if(ctrl[11]) $fwrite(fid,"qam_sel_sideband =%h\n",qam_sel_sideband );
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if(ctrl[12]) $fwrite(fid,"intp_mode =%h\n",intp_mode );
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if(ctrl[13]) $fwrite(fid,"role_sel =%h\n",role_sel );
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if(ctrl[14]) $fwrite(fid,"dac_mode_sel =%h\n",dac_mode_sel );
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if(ctrl[15]) $fwrite(fid,"dout_sel =%h\n",dout_sel );
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endfunction
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endclass : awgreg_trans
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