229 lines
7.5 KiB
Systemverilog
229 lines
7.5 KiB
Systemverilog
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//For awg_regfile, the ROreg: mcu_resr/rtimr/icntr/fsir are updated by the inputs
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//at this clk_posedge due to dff(inputs->regs)
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class awg_refmodel;
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virtual awgreg_if aif;
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virtual spi_if wif;
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virtual sram_if#(25,32) xif;
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//poor-quality register model
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bit[31:0] rm[24];
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//members to be sent to scoreboard
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int rst_error[5];
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bit[31:0] dout[$];
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awgreg_trans awgout[$];
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function new();
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endfunction
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extern task do_imitate();
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extern task RWreg_write (bit[24:0] addr,bit[32:0] din );
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extern task ROreg_update (bit[24:0] addr );
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extern task reg_read (bit[24:0] addr );
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extern task output_trace (bit[24:0] addr );
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endclass : awg_refmodel
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task awg_refmodel::do_imitate();
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int i=0,j=0;
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rm[ 0] = 32'h0; //MCUPARAR0
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rm[ 1] = 32'h0; //MCUPARAR1
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rm[ 2] = 32'h0; //MCUPARAR2
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rm[ 3] = 32'h0; //MCUPARAR3
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rm[ 4] = 32'h0; //MCURESR0
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rm[ 5] = 32'h0; //MCURESR1
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rm[ 6] = 32'h0; //MCURESR2
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rm[ 7] = 32'h0; //MCURESR3
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rm[ 8] = 32'h0; //PTIMR
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rm[ 9] = 32'h0; //ICNTR
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rm[10] = 32'h0; //FSIR
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rm[11] = 32'h0; //MODMR
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rm[12] = 32'h0; //INTPMR
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rm[13] = 32'h0; //MIXNCOR
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rm[14] = 32'h0; //MIXNFCWHR
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rm[15] = 32'h0; //MIXNFCWLR
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rm[16] = 32'h0; //MIXNPHAR
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rm[17] = 32'h0; //MIXMR
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rm[18] = 32'h0; //MIXODTR
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rm[19] = 32'h0; //MIXODFR
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rm[20] = 32'h0; //ROLER
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rm[21] = 32'h0; //MIXNCOSCER
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rm[22] = 32'h0; //MODDOTR
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rm[23] = 32'h0; //STR
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fork
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while(1) begin: write_reg_RW
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@(negedge xif.wren);
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RWreg_write(xif.addr,xif.din);
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end: write_reg_RW
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while(1) begin: update_reg_RO
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ROreg_update(xif.addr);
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end: update_reg_RO
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while(1) begin: read_reg
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@(negedge xif.rden);
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reg_read(xif.addr);
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end: read_reg
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while(1) begin: output_port
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@(negedge xif.wren);
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output_trace(xif.addr);
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end: output_port
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join
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endtask: do_imitate
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task awg_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din);
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//delay caused by decoder
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@(posedge wif.clk);
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case(addr[24: 2])
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23'hC0000: rm[ 0] = din; //MCUPARAR0
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23'hC0001: rm[ 1] = din; //MCUPARAR1
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23'hC0002: rm[ 2] = din; //MCUPARAR2
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23'hC0003: rm[ 3] = din; //MCUPARAR3
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23'hC0040: rm[11] = {rm[11][31: 1],din[0 : 0]}; //MODMR
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23'hC0041: rm[12] = {rm[12][31: 3],din[2 : 0]}; //INTPMR
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23'hC0042: rm[13] = {rm[13][31: 1],din[0 : 0]}; //MIXNCOR
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23'hC0043: rm[14] = din; //MIXNFCWHR
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23'hC0044: rm[15] = {rm[15][31:16],din[31:16]}; //MIXNFCWLR
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23'hC0045: rm[16] = {rm[16][31:16],din[31:16]}; //MIXNPHAR
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23'hC0046: rm[17] = {rm[17][31: 1],din[0 : 0]}; //MIXMR
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23'hC0047: rm[18] = {rm[18][31: 2],din[1 : 0]}; //MIXODTR
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23'hC0048: rm[19] = {rm[19][31: 2],din[1 : 0]}; //MIXODFR
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23'hC004a: rm[20] = {rm[20][31: 2],din[1 : 0]}; //ROLER
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23'hC004b: rm[21] = {rm[21][31: 1],din[0 : 0]}; //MIXNCOSCER
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23'hC004c: rm[22] = {rm[22][31: 1],din[0 : 0]}; //MODDOTR
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endcase
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//$display("addr:%0h",addr);
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//$display("rm:%h",rm[addr[24: 2]]);
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//$display("din:%h",din);
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endtask: RWreg_write
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task awg_refmodel::ROreg_update(bit[24:0] addr);
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@(posedge wif.clk);
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rm[ 4] = aif.mcu_result0 ; //MCURESR0
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rm[ 5] = aif.mcu_result1 ; //MCURESR1
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rm[ 6] = aif.mcu_result2 ; //MCURESR2
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rm[ 7] = aif.mcu_result3 ; //MCURESR3
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rm[ 8] = aif.run_time ; //PTIMR
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rm[ 9] = aif.instr_num ; //ICNTR
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rm[10] = {rm[10][31:2],aif.fb_st_i[1:0]} ; //FSIR
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rm[23] = {rm[23][31:3],aif.bais_q_ov,aif.bais_i_ov,aif.awg_ctrl_fsm_st} ; //STR
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endtask: ROreg_update
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task awg_refmodel::reg_read(bit[24:0] addr);
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//delay caused be decoder
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//@(posedge wif.clk);
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case(addr[24: 2])
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23'hC0000: dout.push_back(rm[ 0]); //MCUPARAR0
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23'hC0001: dout.push_back(rm[ 1]); //MCUPARAR1
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23'hC0002: dout.push_back(rm[ 2]); //MCUPARAR2
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23'hC0003: dout.push_back(rm[ 3]); //MCUPARAR3
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23'hC0004: dout.push_back(rm[ 4]); //MCURESR0
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23'hC0005: dout.push_back(rm[ 5]); //MCURESR1
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23'hC0006: dout.push_back(rm[ 6]); //MCURESR2
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23'hC0007: dout.push_back(rm[ 7]); //MCURESR3
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23'hC0008: dout.push_back(0);
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23'hC0026: dout.push_back(rm[ 8]); //PTIMR
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23'hC0027: dout.push_back(rm[ 9]); //ICNTR
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23'hC0028: dout.push_back(rm[10]); //FSIR
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23'hC0029: dout.push_back(0);
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23'hC0040: dout.push_back(rm[11]); //MODMR
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23'hC0041: dout.push_back(rm[12]); //INTPMR
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23'hC0042: dout.push_back(rm[13]); //MIXNCOR
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23'hC0043: dout.push_back(rm[14]); //MIXNFCWHR
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23'hC0044: dout.push_back(rm[15]); //MIXNFCWLR
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23'hC0045: dout.push_back(rm[16]); //MIXNPHAR
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23'hC0046: dout.push_back(rm[17]); //MIXMR
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23'hC0047: dout.push_back(rm[18]); //MIXODTR
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23'hC0048: dout.push_back(rm[19]); //MIXODFR
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23'hC0049: dout.push_back(0) ;
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23'hC004a: dout.push_back({rm[20][31:2],rm[20][1 : 1]&rm[20][0 :0],rm[20][0 : 0]}); //ROLER
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23'hC004b: dout.push_back(rm[21]); //MIXNCOSCER
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23'hC004c: dout.push_back(rm[22]); //MODDOTR
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23'hC004d: dout.push_back(rm[23]); //STR
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23'hC004e: dout.push_back(0);
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endcase
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//$display("addr:%0h,dout:%h",addr[24:2],dout[$]);
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endtask: reg_read
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task awg_refmodel::output_trace(bit[24:0] addr);
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awgreg_trans tr_temp;
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if(addr[24:20 == 5'h3])
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begin
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//delay caused by decoder
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@(posedge wif.clk);
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@(negedge wif.clk);
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tr_temp = new();
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tr_temp.mcu_param0 = rm[ 0] ; //MCUPARAR0
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tr_temp.mcu_param1 = rm[ 1] ; //MCUPARAR1
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tr_temp.mcu_param2 = rm[ 2] ; //MCUPARAR2
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tr_temp.mcu_param3 = rm[ 3] ; //MCUPARAR3
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tr_temp.fb_st_o = rm[10][1: 0] ; //FSIR
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tr_temp.mod_sel_sideband = rm[11][0: 0] ; //MODMR
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tr_temp.qam_nco_clr = rm[13][0 :0] ; //MIXNCOR
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tr_temp.qam_nco_sclr_en = rm[21][0 :0] ; //MIXNCOSCER
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tr_temp.qam_fcw = {rm[14],rm[15][15:0]} ; //MIXNFCWHR MIXNFCWLR
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tr_temp.qam_pha = rm[16][15: 0] ; //MIXNPHAR
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tr_temp.qam_mod = rm[18][1 : 0] ; //MIXODTR
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tr_temp.qam_sel_sideband = rm[17][0 : 0] ; //MIXMR
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tr_temp.intp_mode = rm[12][2 : 0] ; //INTPMR
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tr_temp.role_sel[0] = rm[20][0 : 0] ; //ROLER[0]
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tr_temp.role_sel[1] = rm[20][1 : 1]&rm[20][0 :0]; //ROLER[1]
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tr_temp.dac_mode_sel = rm[19][1 : 0] ; //MIXODFR
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tr_temp.dout_sel = rm[22][0 : 0] ; //MODDOTR
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awgout.push_back(tr_temp);
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end
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//$display("addr:%0h",addr);
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//$display("rm:%h",rm[addr[24: 2]]);
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//$display("din:%h",din);
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endtask: output_trace
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