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更新管脚和修复寄存器定义

This commit is contained in:
guocheng 2026-02-09 10:15:55 +08:00
parent a86434ef5d
commit 2c23b7b213
4 changed files with 7 additions and 5 deletions
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assets/pin_map.png
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4
ids/读出子系统IDS表.json
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@ -2438,8 +2438,8 @@
"Fields": [
{
"Bits": [
15,
0
31,
16
],
"FieldName": "pcw",
"ResetValue": "16'h0000",

2
pin_loc.csv
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@ -11,4 +11,4 @@ J,DGND,DAQ_GPIO<3>,DGND,LOC_LVCMOS<24>,DIG_VDD,LOC_LVCMOS<25>,LOC_LVCMOS<29>,DGN
K,LOC_LVCMOS<23>,LOC_LVCMOS<26>,LOC_LVCMOS<27>,LOC_LVCMOS<28>,DGND,LOC_LVCMOS<30>,DAQ_GPIO<2>,DGND,ADC_DVDD,ADC_VDD,ADC_VDD18,ADC_VR850,ADC_REF_SENSE
L,DAQ_GPIO<1>,DAQ_GPIO<0>,DGND,DGND,LOC_LVCMOS<31>,PI_SYNC_IN,DGND,DGND,ADC_DVDD,ADC_VDD,ADC_VDD18,ADC_VR350,ADC_VBIAS_IREF_RES
M,DGND,DGND,RSLT_PUSH_P,RSLT_PUSH_N,DGND,DGND,LVDSTX_CLKP,LVDSTX_CLKN,AGND,AGND,AGND,AGND,AGND
N,GLB_FB_TX_P,GLB_FB_TX_N,DGND,DGND,GLB_FB_RX_P,GLB_FB_RX_N,DGND,AGND,ADC_VINN,ADC_VINP,AGND,ADC_VINP,ADC_VINN
N,GLB_FB_TX_P,GLB_FB_TX_N,DGND,DGND,GLB_FB_RX_P,GLB_FB_RX_N,DGND,AGND,ADC_VINN1,ADC_VINP1,AGND,ADC_VINP2,ADC_VINN2

1 1 2 3 4 5 6 7 8 9 10 11 12 13
11 K LOC_LVCMOS<23> LOC_LVCMOS<26> LOC_LVCMOS<27> LOC_LVCMOS<28> DGND LOC_LVCMOS<30> DAQ_GPIO<2> DGND ADC_DVDD ADC_VDD ADC_VDD18 ADC_VR850 ADC_REF_SENSE
12 L DAQ_GPIO<1> DAQ_GPIO<0> DGND DGND LOC_LVCMOS<31> PI_SYNC_IN DGND DGND ADC_DVDD ADC_VDD ADC_VDD18 ADC_VR350 ADC_VBIAS_IREF_RES
13 M DGND DGND RSLT_PUSH_P RSLT_PUSH_N DGND DGND LVDSTX_CLKP LVDSTX_CLKN AGND AGND AGND AGND AGND
14 N GLB_FB_TX_P GLB_FB_TX_N DGND DGND GLB_FB_RX_P GLB_FB_RX_N DGND AGND ADC_VINN ADC_VINN1 ADC_VINP ADC_VINP1 AGND ADC_VINP ADC_VINP2 ADC_VINN ADC_VINN2

6
pin_name.csv
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@ -48,8 +48,10 @@ J12,VCTRL,I/模拟,PLL内部VCO控制电压
F11,BIAS_CAP,/,PLL偏置去耦，接片外电容100n电容
G11,RES_2K,/,PLL接片外电阻2K
A12,PORT_BIAS_TB,O/模拟,PLL加滤波电容，10uF*1，1uF*1，0.1uF*3
N10 N12,ADC_VINP,I/模拟,ADC模拟输入信号
N9 N13,ADC_VINN,^,^
N9,ADC_VINN1,I/模拟,ADC模拟输入信号1组负端
N10,ADC_VINP1,I/模拟,ADC模拟输入信号1组正端
N12,ADC_VINP2,I/模拟,ADC模拟输入信号2组正端
N13,ADC_VINN2,I/模拟,ADC模拟输入信号2组负端
K12,ADC_VR850,I/模拟,ADC外部850 mV参考，需要去耦
L12,ADC_VR350,I/模拟,ADC外部350 mV参考，需要去耦
K13,ADC_REF_SENSE,I/模拟,ADC 带隙电压内外部切换，1.8 V选择内部，0.52V选择外部

1 Pin Number Pin Name Pin Type DISCRIPTION
48 F11 BIAS_CAP / PLL偏置去耦，接片外电容100n电容
49 G11 RES_2K / PLL接片外电阻2K
50 A12 PORT_BIAS_TB O/模拟 PLL加滤波电容，10uF*1，1uF*1，0.1uF*3
51 N10 N12 N9 ADC_VINP ADC_VINN1 I/模拟 ADC模拟输入信号 ADC模拟输入信号1组负端
52 N9 N13 N10 ADC_VINN ADC_VINP1 ^ I/模拟 ^ ADC模拟输入信号1组正端
53 N12 ADC_VINP2 I/模拟 ADC模拟输入信号2组正端
54 N13 ADC_VINN2 I/模拟 ADC模拟输入信号2组负端
55 K12 ADC_VR850 I/模拟 ADC外部850 mV参考，需要去耦
56 L12 ADC_VR350 I/模拟 ADC外部350 mV参考，需要去耦
57 K13 ADC_REF_SENSE I/模拟 ADC 带隙电压内外部切换，1.8 V选择内部，0.52V选择外部