From 25d503c2133f2ee27def44453b711f51628fb73b Mon Sep 17 00:00:00 2001 From: guocheng Date: Thu, 27 Nov 2025 11:43:14 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9B=B4=E6=96=B0=E6=96=87=E6=A1=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 3 +- ids/读出子系统IDS表.json | 20 ++++++------ pin_loc.csv | 14 ++++++++ pin_name.csv | 53 +++++++++++++++++++++++++++++++ 新建 Microsoft Excel 工作表.xlsx | Bin 6604 -> 0 bytes 读出芯片用户使用手册.md | 52 ++++++++++++++++++++++++++++-- 6 files changed, 128 insertions(+), 14 deletions(-) create mode 100644 pin_loc.csv create mode 100644 pin_name.csv delete mode 100644 新建 Microsoft Excel 工作表.xlsx diff --git a/.gitignore b/.gitignore index 27dcd7e..c715390 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ script/读出子系统IDS表.xls -读出芯片用户使用手册.pdf \ No newline at end of file +读出芯片用户使用手册.html +pin_loc.xlsx \ No newline at end of file diff --git a/ids/读出子系统IDS表.json b/ids/读出子系统IDS表.json index 643358a..f54a6f1 100644 --- a/ids/读出子系统IDS表.json +++ b/ids/读出子系统IDS表.json @@ -267,12 +267,12 @@ "SYS_REG": { "StartAddress": "0x00000000", "Size": "64B", - "Info": "读出系统ADC和DAC配置" + "Info": "读出系统整体寄存器配置" }, "SYS_ANA": { "StartAddress": "0x00100000", "Size": "512B", - "Info": "读出系统整体寄存器配置" + "Info": "读出系统ADC和DAC配置" }, "SYS_PLL": { "StartAddress": "0x01F00000", @@ -288,12 +288,12 @@ "SYS_REG": { "StartAddress": "0x00000000", "Size": "64B", - "Info": "读出系统ADC和DAC配置" + "Info": "读出系统整体寄存器配置" }, "SYS_ANA": { "StartAddress": "0x00100000", "Size": "512B", - "Info": "读出系统整体寄存器配置" + "Info": "读出系统ADC和DAC配置" }, "SYS_PLL": { "StartAddress": "0x01F00000", @@ -309,12 +309,12 @@ "SYS_REG": { "StartAddress": "0x00000000", "Size": "64B", - "Info": "读出系统ADC和DAC配置" + "Info": "读出系统整体寄存器配置" }, "SYS_ANA": { "StartAddress": "0x00100000", "Size": "512B", - "Info": "读出系统整体寄存器配置" + "Info": "读出系统ADC和DAC配置" }, "SYS_PLL": { "StartAddress": "0x01F00000", @@ -330,12 +330,12 @@ "SYS_REG": { "StartAddress": "0x00000000", "Size": "64B", - "Info": "读出系统ADC和DAC配置" + "Info": "读出系统整体寄存器配置" }, "SYS_ANA": { "StartAddress": "0x00100000", "Size": "512B", - "Info": "读出系统整体寄存器配置" + "Info": "读出系统ADC和DAC配置" }, "SYS_PLL": { "StartAddress": "0x01F00000", @@ -5538,8 +5538,8 @@ "ResetValue": -200, "Range": { "value": [ - "-1300", - "-200" + "-1100", + "-300" ], "type": "list" }, diff --git a/pin_loc.csv b/pin_loc.csv new file mode 100644 index 0000000..8214ef3 --- /dev/null +++ b/pin_loc.csv @@ -0,0 +1,14 @@ +,1,2,3,4,5,6,7,8,9,10,11,12,13 +A,DGND,LOC_LVCMOS<22>,LOC_LVCMOS<9>,LOC_LVCMOS<1>,DGND,PI_CHIP_ID<0>,DGND,LOC_LVCMOS<0>,AVDD_ENCODER,AGND,CLK_REF_P,CLK_REF_N,AGND +B,LOC_LVCMOS<19>,PO_DEBUG_OUT,DGND,LOC_LVCMOS<7>,IO_VDD,DGND,LOC_LVCMOS<3>,PI_CHIP_ID<1>,AGND,AVDD_ENCODER,AGND,AGND,AVDD_P2S +C,PO_MISO,DGND,PO_INTR_IRQ_N,DGND,IO_VDD,LOC_LVCMOS<4>,LOC_LVCMOS<2>,DGND,DAC_DVDD,DAC_AVDD18,PORT_BIAS_TB,VREF500IN,AVDD_P2S +D,DGND,PI_MOSI,LOC_LVCMOS<18>,PO_PUMP_EN,IO_VDD,LOC_LVCMOS<8>,DGND,DGND,DAC_DVDD,AGND,DAC_AVDD18,DAC_VBIAS_IREF_RES,AGND +E,PI_PB_RST_N,LOC_LVCMOS<15>,LOC_LVCMOS<17>,DGND,DGND,DGND,LOC_LVCMOS<6>,LOC_LVCMOS<5>,AGND,PLL_VDD18,AGND,AGND,DAC_VOUTP +F,DGND,AWG_GPIO<3>,DGND,PI_SCLK,DIG_VDD,LOC_LVCMOS<20>,PO_READ_REQ_N,LOC_LVCMOS<21>,PLL_VDD18,AGND,BIAS_CAP,AGND,DAC_VOUTN +G,AWG_GPIO<2>,DGND,LOC_LVCMOS<13>,LOC_LVCMOS<14>,DIG_VDD,LOC_LVCMOS<16>,PI_CSN,DGND,PLL_DVDD,CP_OUT,RES_2K,VCTRL,AGND +H,LOC_LVCMOS<11>,LOC_LVCMOS<10>,AWG_GPIO<0>,DGND,DIG_VDD,AWG_GPIO<1>,LOC_LVCMOS<12>,DGND,PLL_DVDD,AGND,PLL_VREF520,PLL_VDD,AGND +J,DGND,DAQ_GPIO<3>,DGND,LOC_LVCMOS<24>,DGND,LOC_LVCMOS<25>,LOC_LVCMOS<29>,DGND,VCO_VDD,VCO_VDD,PLL_VDD,AGND,ADC_VINP +K,LOC_LVCMOS<23>,LOC_LVCMOS<26>,LOC_LVCMOS<27>,LOC_LVCMOS<28>,DGND,LOC_LVCMOS<30>,DAQ_GPIO<2>,DGND,ADC_DVDD,AGND,ADC_VDD18,AGND,ADC_VINN +L,DAQ_GPIO<1>,DAQ_GPIO<0>,DGND,DGND,LOC_LVCMOS<31>,PI_SYNC_IN,DGND,DGND,ADC_DVDD,ADC_VDD18,ADC_VDD,ADC_VBIAS_IREF_RES,AGND +M,DGND,DGND,RSLT_PUSH_P,RSLT_PUSH_N,DGND,DGND,GLB_FB_RX_P,GLB_FB_RX_N,DGND,ADC_VDD,AGND,AGND,ADC_REF_SENSE +N,GLB_FB_TX_P,GLB_FB_TX_N,DGND,DGND,LVDSTX_CLKP,LVDSTX_CLKN,DGND,DGND,DGND,AGND,ADC_VR350,ADC_VR850,AGND diff --git a/pin_name.csv b/pin_name.csv new file mode 100644 index 0000000..dfa4653 --- /dev/null +++ b/pin_name.csv @@ -0,0 +1,53 @@ +Pin Number,Pin Type,Pin Name,DISCRIPTION,,,,,,, +F5 G5 H5 C9 D9 G9 H9 K9 L9,POWER,DVDD,数字模块1.0V电源，采用DVDD供电，与其他DVDD作磁珠隔离,,,,,,,9 +B5 C5 D5,POWER,DVDD18,数字模块1.8V电源，采用DVDD18供电,,,,,,,3 +A1 D1 F1 J1 M1 C2 G2 M2 B3 F3 J3 L3 N3 C4 E4 H4 L4 N4 A5 E5 J5 K5 M5 B6 E6 M6 A7 D7 L7 N7 C8 D8 G8 H8 J8 K8 L8 N8 M9 N9,GROUND,DGND,数字模块地，与GND间作磁珠隔离,,,,,,,40 +L10 M10,POWER,ADC_AVDD,ADC模块数字1.0V电源，采用DVDD供电，与其他DVDD作磁珠隔离,,,,,,,2 +K11 L11,POWER,ADC_AVDD18,ADC模块模拟1.8V电源，采用VDD18_1供电,,,,,,,2 +A9 E9 F9 C10 D10 J10 N10 B11 E11 H11 M11 B12 C12 E12 G12 H12 K12 M12 A13 D13 F13 J13 N13,GROUND,AGND,模拟地,,,,,,,23 +J9 K10 F11 F12,POWER,PLL_AVDD,PLL模块模拟1.0V电源，采用VDD_2供电，与其他VDD_2作磁珠隔离,,,,,,,4 +159,POWER,VCO_VDD,VCO模块模拟1.0V电源，采用VDD_2供电，与其他VDD_2作磁珠隔离,,,,,,, +E10 F10,POWER,PLL_VDD18,PLL模块模拟1.8V电源，采用VDD18_2供电,,,,,,,2 +144 155,GROUND,PLL_GND,PLL模块模拟地，采用全局地GND,,,,,,, +148,GROUND,PLL_DGND,PLL模块数字地，与GND间作磁珠隔离,,,,,,, +157 158,GROUND,VCO_GND,VCO模块模拟地，采用全局地GND,,,,,,, +193 194 197 198 201 202 205 206,POWER,AVDD_P2S,DAC模块模拟1.0V电源，采用VDD_3供电，与其他VDD_3作磁珠隔离,,,,,,, +181 184 187 190 ,POWER,AVDD_ENCODER,DAC模块模拟1.0V电源，采用VDD_3供电，与其他VDD_3作磁珠隔离,,,,,,, +163,POWER,DAC_DVDD,DAC模块数字1.0V电源，采用DVDD供电，与其他DVDD作磁珠隔离,,,,,,, +179 182 185 188,POWER,DAC_AVDD18,DAC模块模拟1.8V电源，采用VDD18_3供电,,,,,,, +165 166 167 169 171 172 173 174,GROUND,DAC_AGND,DAC模块模拟地，采用全局地GND,,,,,,, +178 191 195 199 203,GROUND,DAC_AGND_S,DAC模块模拟地S，采用全局地GND,,,,,,, +180 183 186 189,GROUND,AGND_ENCODER,ENCODER模块模拟地，采用全局地GND,,,,,,, +192 196 200 204,GROUND,AGND_P2S,P2S模块模拟地，采用全局地GND,,,,,,, +164 175 176 177,GROUND,DAC_DGND,DAC模块数字地，与GND间作磁珠隔离,,,,,,, +B1 C1 E1 G1 H1 K1 L1 A2 B2 D2 E2 F2 H2 J2 K2 L2 A3 C3 D3 E3 G3 H3 K3 A4 B4 D4 F4 G4 J4 K4 L5 L6,O/数字,loc_lvcmos<0:31>,loc_lvcmos[q*2+1:q*2]为解模频点q的反馈结果，00、01、10、11电平分别对应0、1、2态和未定义态,,,,,,,32 +D6 C7,I/数字,pi_chip_id<0:1>,读出芯片的ID编号，可通过200欧电阻接I/O电源或地来设置芯片ID编号。,,,,,,,2 +A6,O/数字,po_debug_out,内部调试信号输出，不用的话1k电阻接地,,,,,,,1 +C6,O/数字,po_pump_en,Pump使能信号输出,,,,,,,1 +B7,OD/数字,po_read_req_n,数字开漏输出，上拉接控制器，读请求低有效,,,,,,,1 +B8,OD/数字,po_intr_irq_n,数字开漏输出，上拉接控制器，异常请求低有效,,,,,,,1 +A8, O/数字,po_miso, spi数据输出，接4.7k上拉电阻到I/O电源,,,,,,,1 +F6, I/数字,pi_mosi, spi数据输入，接4.7k上拉电阻到I/O电源,,,,,,,1 +F7, I/数字,pi_csn, spi芯片片选，接4.7k上拉电阻到I/O电源,,,,,,,1 +F8,SPI/数字,pi_sclk , spi芯片时钟，接4.7k上拉电阻到I/O电源,,,,,,,1 +E8,I/数字,pi_pb_rst_n,芯片复位信号，低有效,,,,,,,1 +E7,I/数字,pi_sync_in,芯片同步触发信号，高有效,,,,,,,1 +G7 H7 J7 K7, IO/数字, awg_gpio<3:0>, awg预留GPIO,,,,,,,4 +G6 H6 J6 K6, IO/数字, daq_gpio<3:0>, daq预留GPIO,,,,,,,4 +N1 N2,O/数字,GLB_FB_TX_P/N,反馈结果数据发送接口,,,,,,,2 +M3 M4,O/数字,RSLT_PUSH_P/N,采集结果数据发送接口,,,,,,,2 +M7 M8,I/数字,GLB_FB_RX_P/N,反馈结果数据接收接口,,,,,,,2 +N5 N6,O/数字,LVDSTX_CLKP/N,时钟信号0-1V，0-750MHz,,,,,,, +N11 N12,I/模拟,ADC_VINN/P_A/B,ADC输入信号,,,,,,,2 +133 134,I/模拟,ADC_VR350 ADC_VR850,基准电压0.35/0.85V，需要去偶,,,,,,, +136,I/模拟,ADC_VBIAS_IREF_RES,偏置电路基准电流，外接5.2K电阻，并联10 uF去耦电容。,,,,,,, +137,I/模拟,ADC_REF_SENSE,Bandgap电压内外部切换，1.8 V选择内部Bandgap，0.52V选择外部Bandgap,,,,,,, +146 147,I/模拟,CLK_REF_P/N,PLL参考时钟输入，频率范围：,,,,,,, +150,I/模拟,PLL_VREF520,外部520 mV偏置电压，需要去偶,,,,,,, +151 154,IO/模拟,CP_OUT VCTRL,接片外滤波器,,,,,,, +153,/,BIAS_CAP,接片外电容100n,,,,,,, +H10,/,RES_2K,接片外电阻2K,,,,,,,1 +A10,I/模拟,VREF500IN,外部500 mV偏置电压，需要去偶,,,,,,,1 +A12,O/模拟,DAC_VBIAS_IREF_RES,接5KΩ电阻到地，需要去偶,,,,,,,1 +A11,O/模拟,PORT_BIAS_TB,加滤波电容，10uF*1，1uF*1，0.1uF*3,,,,,,,1 +B13 C13,O/模拟,DAC_VOUTP/N,内部为50Ω电阻网络，外部。。。,,,,,,,2 diff --git a/新建 Microsoft Excel 工作表.xlsx b/新建 Microsoft Excel 工作表.xlsx deleted file mode 100644 index fd7feff1d742fc8c9fd98cc20d3d6ff0cb219743..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6604 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INT_STATUS寄存器是INT_MASK与对应实际输入状态按位相与再与INS_STATUS本身按位或运算的结果，需要通过命令清零。 @@ -221,8 +267,7 @@ MCU模块仅能够访问模块内部的控制器指令、控制器数据和寄 * 注3：匹配滤波器参数和匹配滤波器权重分别对应FPGA和ASIC平台， FPGA平台受限于计算资源有限，采用系数直接存储的方案， 需要额外配置0x580000地址数据，此时0x500000地址中仅包络参数有效。 - - +* 注4：系统状态配置、模拟配置状态、PLL配置状态属于运维寄存器，实验时禁止修改。实验只需要修改DAQ配置状态和AWG配置状态。 ## 8.2 操作码字定义 @@ -237,3 +282,4 @@ FPGA平台受限于计算资源有限，采用系数直接存储的方案， 相应的驱动软件配置文件参考[读出芯片IDS表](ids/读出子系统IDS表.json)。 # 9. 芯片尺寸 +TODO \ No newline at end of file